[PATCH] D54583: PowerPC: Optimize SPE double parameter calling setup

[Kei Thomsen via Phabricator via llvm-commits]

kthomsen added a comment.

I have a question:
When compiling

double a;
void func(double x) {
a = x;
}

It is generating

lis 5, a at ha
evstdd 3, a at l(5)

But as the evstdd and evldd are having only 8bit (5bit real) UIMM offset, this code is not working, as the offset a at lo is not known to be 8bit only.
Is this issue already addressed in a patch and I simply haven't seen this, or is this still a missing part?

I would expect

lis 5, a at ha
li 4, a at l
evstddx 3, 4, 5

It seems that this is checked/generated by the PPCISelLowering.cpp SelectAddressRegReg() and/or SelectAddressRegImm()
Actually I'm trying to find out I have enough information in the SDValue N to identify this as a SPE load/store.
Do I missed a patch for this?
Thanks, Kei


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