[llvm] r351591 - GlobalISel: Verify G_ICMP/G_FCMP vector types

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri Jan 18 12:49:17 2019
New Revision: 351591

URL: http://llvm.org/viewvc/llvm-project?rev=351591&view=rev
Log:
GlobalISel: Verify G_ICMP/G_FCMP vector types

Added:
    llvm/trunk/test/Verifier/test_g_fcmp.mir
    llvm/trunk/test/Verifier/test_g_icmp.mir
Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=351591&r1=351590&r2=351591&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Jan 18 12:49:17 2019
@@ -1187,6 +1187,17 @@ void MachineVerifier::visitMachineInstrB
     }
     break;
   }
+  case TargetOpcode::G_ICMP:
+  case TargetOpcode::G_FCMP: {
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+    LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
+
+    if ((DstTy.isVector() != SrcTy.isVector()) ||
+        (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
+      report("Generic vector icmp/fcmp must preserve number of lanes", MI);
+
+    break;
+  }
   case TargetOpcode::STATEPOINT:
     if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
         !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||

Added: llvm/trunk/test/Verifier/test_g_fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Verifier/test_g_fcmp.mir?rev=351591&view=auto
==============================================================================
--- llvm/trunk/test/Verifier/test_g_fcmp.mir (added)
+++ llvm/trunk/test/Verifier/test_g_fcmp.mir Fri Jan 18 12:49:17 2019
@@ -0,0 +1,40 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_fcmp
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    %0:_(s32) = G_FCONSTANT float 0.0
+    %1:_(s32) = G_FCONSTANT float 1.0
+
+   ; Vector result, scalar source
+   ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
+    %2:_(<2 x s1>) = G_FCMP floatpred(oeq), %0, %1
+
+    ; Scalar result, vector source
+    ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
+    %3:_(<2 x s32>) = G_IMPLICIT_DEF
+    %4:_(<2 x s32>) = G_IMPLICIT_DEF
+    %5:_(s1) = G_FCMP floatpred(oeq), %3, %4
+
+    ; mismatched element count
+    ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of
+    %6:_(<2 x s32>) = G_IMPLICIT_DEF
+    %7:_(<2 x s32>) = G_IMPLICIT_DEF
+    %8:_(<4 x s1>) = G_FCMP floatpred(oeq), %6, %7
+
+
+    ; mismatched scalar element type
+    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+    %9:_(s32) = G_FCONSTANT float 0.0
+    %10:_(s64) = G_FCONSTANT float 1.0
+    %11:_(s1) = G_FCMP floatpred(oeq), %9, %10
+
+...

Added: llvm/trunk/test/Verifier/test_g_icmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Verifier/test_g_icmp.mir?rev=351591&view=auto
==============================================================================
--- llvm/trunk/test/Verifier/test_g_icmp.mir (added)
+++ llvm/trunk/test/Verifier/test_g_icmp.mir Fri Jan 18 12:49:17 2019
@@ -0,0 +1,40 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_icmp
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+
+   ; Vector result, scalar source
+   ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
+    %2:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1
+
+    ; Scalar result, vector source
+    ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
+    %3:_(<2 x s32>) = G_IMPLICIT_DEF
+    %4:_(<2 x s32>) = G_IMPLICIT_DEF
+    %5:_(s1) = G_ICMP intpred(eq), %3, %4
+
+    ; mismatched element count
+    ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of
+    %6:_(<2 x s32>) = G_IMPLICIT_DEF
+    %7:_(<2 x s32>) = G_IMPLICIT_DEF
+    %8:_(<4 x s1>) = G_ICMP intpred(eq), %6, %7
+
+
+    ; mismatched scalar element type
+    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
+    %9:_(s32) = G_CONSTANT i32 0
+    %10:_(s64) = G_CONSTANT i32 1
+    %11:_(s1) = G_ICMP intpred(eq), %9, %10
+
+...