[llvm] r351527 - [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent

[Shiva Chen via llvm-commits]

Author: shiva
Date: Fri Jan 18 00:36:06 2019
New Revision: 351527

URL: http://llvm.org/viewvc/llvm-project?rev=351527&view=rev
Log:
[ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent

We should not pre-scheduled the node has ADJCALLSTACKDOWN parent,
or else, when bottom-up scheduling, ADJCALLSTACKDOWN and
ADJCALLSTACKUP may hold CallResource too long and make other
calls can't be scheduled. If there's no other available node
to schedule, the scheduler will try to rename the register by
creating copy to avoid the conflict which will fail because
CallResource is not a real physical register.

Added:
    llvm/trunk/test/CodeGen/AVR/pre-schedule.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=351527&r1=351526&r2=351527&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Jan 18 00:36:06 2019
@@ -2939,6 +2939,29 @@ void RegReductionPQBase::PrescheduleNode
             (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
         continue;
 
+    SDNode *PredFrameSetup = nullptr;
+    for (const SDep &Pred : SU.Preds)
+      if (Pred.isCtrl() && Pred.getSUnit()) {
+        // Find the predecessor which is not data dependence.
+        SDNode *PredND = Pred.getSUnit()->getNode();
+
+        // If PredND is FrameSetup, we should not pre-scheduled the node,
+        // or else, when bottom up scheduling, ADJCALLSTACKDOWN and
+        // ADJCALLSTACKUP may hold CallResource too long and make other
+        // calls can't be scheduled. If there's no other available node
+        // to schedule, the schedular will try to rename the register by
+        // creating copy to avoid the conflict which will fail because
+        // CallResource is not a real physical register.
+        if (PredND && PredND->isMachineOpcode() &&
+            (PredND->getMachineOpcode() == TII->getCallFrameSetupOpcode())) {
+          PredFrameSetup = PredND;
+          break;
+        }
+      }
+    // Skip the node has FrameSetup parent.
+    if (PredFrameSetup != nullptr)
+      continue;
+
     // Locate the single data predecessor.
     SUnit *PredSU = nullptr;
     for (const SDep &Pred : SU.Preds)

Added: llvm/trunk/test/CodeGen/AVR/pre-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pre-schedule.ll?rev=351527&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pre-schedule.ll (added)
+++ llvm/trunk/test/CodeGen/AVR/pre-schedule.ll Fri Jan 18 00:36:06 2019
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+target triple = "avr-unknown-unknown"
+
+; The case illustrate DAG schedular may pre-schedule the node has
+; ADJCALLSTACKDOWN parent, so ADJCALLSTACKUP may hold CallResource too long
+; and make other calls can't be scheduled. If there's no other available node
+; to schedule, the scheduler will try to rename the register by creating the
+; copy to avoid the conflict which will fail because CallResource is not a real
+; physical register.
+;
+; The issue is found by Tim on https://github.com/avr-rust/rust/issues/111 and
+; discuss in http://lists.llvm.org/pipermail/llvm-dev/2018-October/127083.html.
+
+define void @"main"() addrspace(1) {
+start:
+  %0 = or i64 undef, undef
+   br i1 undef, label %mul_and_call, label %fail
+
+  mul_and_call:
+  %1 = mul i64 %0, %0
+  call addrspace(1) void @"three_ints"(i64 undef, i64 %1, i64 %0)
+; The CHECK line only want to make sure the following assertion message
+; won't trigger due to create copy of artificial CallResource register.
+; llc: llvm/lib/CodeGen/TargetRegisterInfo.cpp:203: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::MVT) const: Assertion `BestRC && "Couldn't find the register class"' failed.
+; CHECK: call    __muldi3
+  ret void
+
+  fail:
+    ret void
+}
+
+declare void @"three_ints"(i64, i64, i64) addrspace(1)