[llvm] r351066 - [X86] Add add/sub saturation undef tests.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 14 05:47:07 PST 2019
Author: rksimon
Date: Mon Jan 14 05:47:07 2019
New Revision: 351066
URL: http://llvm.org/viewvc/llvm-project?rev=351066&view=rev
Log:
[X86] Add add/sub saturation undef tests.
Modified:
llvm/trunk/test/CodeGen/X86/combine-add-ssat.ll
llvm/trunk/test/CodeGen/X86/combine-add-usat.ll
llvm/trunk/test/CodeGen/X86/combine-sub-ssat.ll
llvm/trunk/test/CodeGen/X86/combine-sub-usat.ll
Modified: llvm/trunk/test/CodeGen/X86/combine-add-ssat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-add-ssat.ll?rev=351066&r1=351065&r2=351066&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-add-ssat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-add-ssat.ll Mon Jan 14 05:47:07 2019
@@ -11,6 +11,36 @@ declare i32 @llvm.sadd.sat.i32 (i32, i
declare i64 @llvm.sadd.sat.i64 (i64, i64)
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
+; fold (sadd_sat x, undef) -> -1
+define i32 @combine_undef_i32(i32 %a0) {
+; CHECK-LABEL: combine_undef_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: addl %eax, %ecx
+; CHECK-NEXT: setns %al
+; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-NEXT: addl %eax, %edi
+; CHECK-NEXT: cmovnol %edi, %eax
+; CHECK-NEXT: retq
+ %res = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 undef)
+ ret i32 %res
+}
+
+define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
+; SSE-LABEL: combine_undef_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: paddsw %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_undef_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpaddsw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
+ ret <8 x i16> %res
+}
+
; fold (sadd_sat c1, c2) -> c3
define i32 @combine_constfold_i32() {
; CHECK-LABEL: combine_constfold_i32:
Modified: llvm/trunk/test/CodeGen/X86/combine-add-usat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-add-usat.ll?rev=351066&r1=351065&r2=351066&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-add-usat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-add-usat.ll Mon Jan 14 05:47:07 2019
@@ -11,6 +11,32 @@ declare i32 @llvm.uadd.sat.i32 (i32, i
declare i64 @llvm.uadd.sat.i64 (i64, i64)
declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
+; fold (uadd_sat x, undef) -> -1
+define i32 @combine_undef_i32(i32 %a0) {
+; CHECK-LABEL: combine_undef_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addl %eax, %edi
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovael %edi, %eax
+; CHECK-NEXT: retq
+ %res = call i32 @llvm.uadd.sat.i32(i32 %a0, i32 undef)
+ ret i32 %res
+}
+
+define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
+; SSE-LABEL: combine_undef_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: paddusw %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_undef_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpaddusw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
+ ret <8 x i16> %res
+}
+
; fold (uadd_sat c1, c2) -> c3
define i32 @combine_constfold_i32() {
; CHECK-LABEL: combine_constfold_i32:
Modified: llvm/trunk/test/CodeGen/X86/combine-sub-ssat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sub-ssat.ll?rev=351066&r1=351065&r2=351066&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sub-ssat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sub-ssat.ll Mon Jan 14 05:47:07 2019
@@ -11,13 +11,43 @@ declare i32 @llvm.ssub.sat.i32 (i32, i
declare i64 @llvm.ssub.sat.i64 (i64, i64)
declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
+; fold (ssub_sat x, undef) -> 0
+define i32 @combine_undef_i32(i32 %a0) {
+; CHECK-LABEL: combine_undef_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: setns %al
+; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-NEXT: subl %eax, %edi
+; CHECK-NEXT: cmovnol %edi, %eax
+; CHECK-NEXT: retq
+ %res = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 undef)
+ ret i32 %res
+}
+
+define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
+; SSE-LABEL: combine_undef_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: psubsw %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_undef_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpsubsw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
+ ret <8 x i16> %res
+}
+
; fold (ssub_sat c, 0) -> x
define i32 @combine_zero_i32(i32 %a0) {
; CHECK-LABEL: combine_zero_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
- %1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 0);
+ %1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 0)
ret i32 %1
}
@@ -25,6 +55,6 @@ define <8 x i16> @combine_zero_v8i16(<8
; CHECK-LABEL: combine_zero_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
- %1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer);
+ %1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)
ret <8 x i16> %1
}
Modified: llvm/trunk/test/CodeGen/X86/combine-sub-usat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sub-usat.ll?rev=351066&r1=351065&r2=351066&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sub-usat.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sub-usat.ll Mon Jan 14 05:47:07 2019
@@ -11,13 +11,39 @@ declare i32 @llvm.usub.sat.i32 (i32, i
declare i64 @llvm.usub.sat.i64 (i64, i64)
declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
+; fold (usub_sat x, undef) -> 0
+define i32 @combine_undef_i32(i32 %a0) {
+; CHECK-LABEL: combine_undef_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: subl %eax, %edi
+; CHECK-NEXT: cmovael %edi, %eax
+; CHECK-NEXT: retq
+ %res = call i32 @llvm.usub.sat.i32(i32 %a0, i32 undef)
+ ret i32 %res
+}
+
+define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
+; SSE-LABEL: combine_undef_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: psubusw %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_undef_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpsubusw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %res = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
+ ret <8 x i16> %res
+}
+
; fold (usub_sat c, 0) -> x
define i32 @combine_zero_i32(i32 %a0) {
; CHECK-LABEL: combine_zero_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
- %1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 0);
+ %1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 0)
ret i32 %1
}
@@ -25,6 +51,6 @@ define <8 x i16> @combine_zero_v8i16(<8
; CHECK-LABEL: combine_zero_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
- %1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer);
+ %1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)
ret <8 x i16> %1
}
More information about the llvm-commits
mailing list