[llvm] r351026 - [DAGCombiner] If add_sat(x, y) can't overflow -> add(x, y)

[Simon Pilgrim via llvm-commits]

Yes, ValueTracking has handlers for signed/unsigned add/sub/mul that 
handle a broader range of cases - instcombine should probably use these 
as part of the sat intrinsic combines.

I'm not sure we need all of that in DAG, we just need to focus on the 
cases that are likely if the sat instructions are generated there, 
especially as I've started looking at PR40111 (move the X86 sat combines 
into DAGCombiner), plus Nikita Popov's work on improving vector support 
(D56636).

On 13/01/2019 23:06, Craig Topper wrote:
> Do we also do this in InstCombine? Is InstCombine's overflow detection 
> more powerful?
>
> ~Craig
>
>
> On Sun, Jan 13, 2019 at 2:12 PM Simon Pilgrim via llvm-commits 
> <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
>
>     Author: rksimon
>     Date: Sun Jan 13 14:08:26 2019
>     New Revision: 351026
>
>     URL: http://llvm.org/viewvc/llvm-project?rev=351026&view=rev
>     Log:
>     [DAGCombiner] If add_sat(x,y) can't overflow -> add(x,y)
>
>     NOTE: We need more powerful signed overflow detection in
>     computeOverflowKind
>
>     Modified:
>         llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>         llvm/trunk/test/CodeGen/X86/combine-add-usat.ll
>
>     Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>     URL:
>     http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=351026&r1=351025&r2=351026&view=diff
>     ==============================================================================
>     --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>     +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jan 13
>     14:08:26 2019
>     @@ -2206,6 +2206,10 @@ SDValue DAGCombiner::visitADDSAT(SDNode
>        if (isNullConstant(N1))
>          return N0;
>
>     +  // If it cannot overflow, transform into an add.
>     +  if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
>     +    return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
>     +
>        return SDValue();
>      }
>
>
>     Modified: llvm/trunk/test/CodeGen/X86/combine-add-usat.ll
>     URL:
>     http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-add-usat.ll?rev=351026&r1=351025&r2=351026&view=diff
>     ==============================================================================
>     --- llvm/trunk/test/CodeGen/X86/combine-add-usat.ll (original)
>     +++ llvm/trunk/test/CodeGen/X86/combine-add-usat.ll Sun Jan 13
>     14:08:26 2019
>     @@ -59,11 +59,11 @@ define <8 x i16> @combine_zero_v8i16(<8
>      define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) {
>      ; CHECK-LABEL: combine_no_overflow_i32:
>      ; CHECK:       # %bb.0:
>     +; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
>     +; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
>      ; CHECK-NEXT:    shrl $16, %edi
>      ; CHECK-NEXT:    shrl $16, %esi
>     -; CHECK-NEXT:    addl %edi, %esi
>     -; CHECK-NEXT:    movl $-1, %eax
>     -; CHECK-NEXT:    cmovael %esi, %eax
>     +; CHECK-NEXT:    leal (%rsi,%rdi), %eax
>      ; CHECK-NEXT:    retq
>        %1 = lshr i32 %a0, 16
>        %2 = lshr i32 %a1, 16
>     @@ -76,14 +76,14 @@ define <8 x i16> @combine_no_overflow_v8
>      ; SSE:       # %bb.0:
>      ; SSE-NEXT:    psrlw $10, %xmm0
>      ; SSE-NEXT:    psrlw $10, %xmm1
>     -; SSE-NEXT:    paddusw %xmm1, %xmm0
>     +; SSE-NEXT:    paddw %xmm1, %xmm0
>      ; SSE-NEXT:    retq
>      ;
>      ; AVX-LABEL: combine_no_overflow_v8i16:
>      ; AVX:       # %bb.0:
>      ; AVX-NEXT:    vpsrlw $10, %xmm0, %xmm0
>      ; AVX-NEXT:    vpsrlw $10, %xmm1, %xmm1
>     -; AVX-NEXT:    vpaddusw %xmm1, %xmm0, %xmm0
>     +; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
>      ; AVX-NEXT:    retq
>        %1 = lshr <8 x i16> %a0, <i16 10, i16 10, i16 10, i16 10, i16
>     10, i16 10, i16 10, i16 10>
>        %2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10, i16 10, i16
>     10, i16 10, i16 10, i16 10>
>
>
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