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<p>Yes, ValueTracking has handlers for signed/unsigned add/sub/mul
that handle a broader range of cases - instcombine should probably
use these as part of the sat intrinsic combines.<br>
</p>
<p>I'm not sure we need all of that in DAG, we just need to focus on
the cases that are likely if the sat instructions are generated
there, especially as I've started looking at PR40111 (move the X86
sat combines into DAGCombiner), plus Nikita Popov's work on
improving vector support (D56636).<br>
</p>
<div class="moz-cite-prefix">On 13/01/2019 23:06, Craig Topper
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:CAF7ks-MWpVDV8AqwhLSTbuLs5OUxgEq0-qha5q-hBLB21=qGwA@mail.gmail.com">
<meta http-equiv="content-type" content="text/html; charset=UTF-8">
<div dir="ltr">Do we also do this in InstCombine? Is InstCombine's
overflow detection more powerful?
<div><br clear="all">
<div>
<div dir="ltr" class="gmail_signature"
data-smartmail="gmail_signature">~Craig</div>
</div>
<br>
</div>
</div>
<br>
<div class="gmail_quote">
<div dir="ltr">On Sun, Jan 13, 2019 at 2:12 PM Simon Pilgrim via
llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org"
moz-do-not-send="true">llvm-commits@lists.llvm.org</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0px 0px 0px
0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author:
rksimon<br>
Date: Sun Jan 13 14:08:26 2019<br>
New Revision: 351026<br>
<br>
URL: <a
href="http://llvm.org/viewvc/llvm-project?rev=351026&view=rev"
rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project?rev=351026&view=rev</a><br>
Log:<br>
[DAGCombiner] If add_sat(x,y) can't overflow -> add(x,y)<br>
<br>
NOTE: We need more powerful signed overflow detection in
computeOverflowKind<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/X86/combine-add-usat.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=351026&r1=351025&r2=351026&view=diff"
rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=351026&r1=351025&r2=351026&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
(original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun
Jan 13 14:08:26 2019<br>
@@ -2206,6 +2206,10 @@ SDValue DAGCombiner::visitADDSAT(SDNode<br>
if (isNullConstant(N1))<br>
return N0;<br>
<br>
+ // If it cannot overflow, transform into an add.<br>
+ if (DAG.computeOverflowKind(N0, N1) ==
SelectionDAG::OFK_Never)<br>
+ return DAG.getNode(ISD::ADD, DL, VT, N0, N1);<br>
+<br>
return SDValue();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/combine-add-usat.ll<br>
URL: <a
href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-add-usat.ll?rev=351026&r1=351025&r2=351026&view=diff"
rel="noreferrer" target="_blank" moz-do-not-send="true">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-add-usat.ll?rev=351026&r1=351025&r2=351026&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/combine-add-usat.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/combine-add-usat.ll Sun Jan 13
14:08:26 2019<br>
@@ -59,11 +59,11 @@ define <8 x i16>
@combine_zero_v8i16(<8<br>
define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) {<br>
; CHECK-LABEL: combine_no_overflow_i32:<br>
; CHECK: # %bb.0:<br>
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi<br>
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi<br>
; CHECK-NEXT: shrl $16, %edi<br>
; CHECK-NEXT: shrl $16, %esi<br>
-; CHECK-NEXT: addl %edi, %esi<br>
-; CHECK-NEXT: movl $-1, %eax<br>
-; CHECK-NEXT: cmovael %esi, %eax<br>
+; CHECK-NEXT: leal (%rsi,%rdi), %eax<br>
; CHECK-NEXT: retq<br>
%1 = lshr i32 %a0, 16<br>
%2 = lshr i32 %a1, 16<br>
@@ -76,14 +76,14 @@ define <8 x i16>
@combine_no_overflow_v8<br>
; SSE: # %bb.0:<br>
; SSE-NEXT: psrlw $10, %xmm0<br>
; SSE-NEXT: psrlw $10, %xmm1<br>
-; SSE-NEXT: paddusw %xmm1, %xmm0<br>
+; SSE-NEXT: paddw %xmm1, %xmm0<br>
; SSE-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_no_overflow_v8i16:<br>
; AVX: # %bb.0:<br>
; AVX-NEXT: vpsrlw $10, %xmm0, %xmm0<br>
; AVX-NEXT: vpsrlw $10, %xmm1, %xmm1<br>
-; AVX-NEXT: vpaddusw %xmm1, %xmm0, %xmm0<br>
+; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0<br>
; AVX-NEXT: retq<br>
%1 = lshr <8 x i16> %a0, <i16 10, i16 10, i16 10,
i16 10, i16 10, i16 10, i16 10, i16 10><br>
%2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10,
i16 10, i16 10, i16 10, i16 10, i16 10><br>
<br>
<br>
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</blockquote>
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