[PATCH] D56281: [DAGCombiner] reduce buildvec of zexted extracted element to shuffle

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:16136
+  SDValue Zext = BV->getOperand(ZextElt);
+  if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() ||
+      Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
----------------
Should ANY_EXTEND be handled as well? SimplifyDemandedBits can reduce ZERO_EXTEND -> ANY_EXTEND more aggressively these days.


================
Comment at: test/CodeGen/X86/buildvec-extract.ll:422
+; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[6,7]
 ; AVX-NEXT:    retq
   %e = extractelement <8 x i16> %x, i32 1
----------------
Please can you investigate what's happening here? The xmm0[6,7] at the end seems really weird....


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56281/new/

https://reviews.llvm.org/D56281