[llvm] r350976 - [AArch64] Improve Exynos predicates

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Fri Jan 11 14:39:47 2019
New Revision: 350976

URL: http://llvm.org/viewvc/llvm-project?rev=350976&view=rev
Log:
[AArch64] Improve Exynos predicates

Expand the predicate using shifted arithmetic and logic instructions to also
consider the respective not shifted instructions.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td?rev=350976&r1=350975&r2=350976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td Fri Jan 11 14:39:47 2019
@@ -48,7 +48,10 @@ def ExynosArithFn   : TIIPredicate<
                                                CheckExtBy3]>]>]>>>,
                            MCOpcodeSwitchCase<
                              IsArithShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
+                             MCReturnStatement<ExynosCheckShift>>,
+                           MCOpcodeSwitchCase<
+                             IsArithUnshiftOp.ValidOpcodes,
+                             MCReturnStatement<TruePred>>],
                           MCReturnStatement<FalsePred>>>;
 def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
 
@@ -58,7 +61,10 @@ def ExynosLogicFn   : TIIPredicate<
                         MCOpcodeSwitchStatement<
                           [MCOpcodeSwitchCase<
                              IsLogicShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
+                             MCReturnStatement<ExynosCheckShift>>,
+                           MCOpcodeSwitchCase<
+                             IsLogicUnshiftOp.ValidOpcodes,
+                             MCReturnStatement<TruePred>>],
                           MCReturnStatement<FalsePred>>>;
 def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
 
@@ -73,7 +79,10 @@ def ExynosLogicExFn   : TIIPredicate<
                                    [ExynosCheckShift,
                                     CheckAll<
                                      [CheckShiftLSL,
-                                      CheckShiftBy8]>]>>>],
+                                      CheckShiftBy8]>]>>>,
+                             MCOpcodeSwitchCase<
+                               IsLogicUnshiftOp.ValidOpcodes,
+                               MCReturnStatement<TruePred>>],
                             MCReturnStatement<FalsePred>>>;
 def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;