[PATCH] D56201: [LegalizeVectorTypes] Allow single loads and stores for more short vectors

[Guillaume Marques via Phabricator via llvm-commits]

tauril marked 3 inline comments as done.
tauril added inline comments.


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Comment at: test/CodeGen/AMDGPU/load-constant-i16.ll:197
-; EG-DAG: 65535
-; EG-DAG: 65535
 define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
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jvesely wrote:
> is there any reason to remove these lines from the test?
I removed these lines from the test because the generated code no longer has them in it.


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Comment at: test/CodeGen/AMDGPU/load-global-i16.ll:201
-; TODO: This should use DST, but for some there are redundant MOVs
-; EGCM: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
 ; EGCM: 16
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jvesely wrote:
> have the extra moves been eliminated by this patch? if not, is there another reason to remove these lines?
Exactly, the moves have been eliminated by the patch!


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Comment at: test/CodeGen/AMDGPU/load-global-i16.ll:222
-; TODO: This should use DST, but for some there are redundant MOVs
-; EGCM-DAG: ASHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
 ; EGCM-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
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jvesely wrote:
> same here
Same thing here, the patch removed these lines from the generated code.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56201/new/

https://reviews.llvm.org/D56201