[PATCH] D56201: [LegalizeVectorTypes] Allow single loads and stores for more short vectors

[Jan Vesely via Phabricator via llvm-commits]

jvesely added a subscriber: arsenm.
jvesely added a comment.

Hi,

sorry for the delay. afaik r600 does not do any special handling wrt to coalescing loads. There is a general load/store vectorizer by @arsenm, so it looks like this patch is interfering with it, but I'd expect the same to happen for GCN as well.
I'm OK with these pessimizations, R600 loads/stores have bigger problems.

jan



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Comment at: test/CodeGen/AMDGPU/load-constant-i16.ll:197
-; EG-DAG: 65535
-; EG-DAG: 65535
 define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
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is there any reason to remove these lines from the test?


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Comment at: test/CodeGen/AMDGPU/load-global-i16.ll:201
-; TODO: This should use DST, but for some there are redundant MOVs
-; EGCM: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
 ; EGCM: 16
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have the extra moves been eliminated by this patch? if not, is there another reason to remove these lines?


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Comment at: test/CodeGen/AMDGPU/load-global-i16.ll:222
-; TODO: This should use DST, but for some there are redundant MOVs
-; EGCM-DAG: ASHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
 ; EGCM-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
----------------
same here


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56201/new/

https://reviews.llvm.org/D56201