[llvm] r350593 - AMDGPU/GlobalISel: Disallow VGPR->SCC copies
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 7 17:13:20 PST 2019
Author: arsenm
Date: Mon Jan 7 17:13:20 2019
New Revision: 350593
URL: http://llvm.org/viewvc/llvm-project?rev=350593&view=rev
Log:
AMDGPU/GlobalISel: Disallow VGPR->SCC copies
This fixes using scalar adds when only the carry in is a VGPR
using greedy regbankselect.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=350593&r1=350592&r2=350593&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Jan 7 17:13:20 2019
@@ -74,13 +74,19 @@ unsigned AMDGPURegisterBankInfo::copyCos
const RegisterBank &Src,
unsigned Size) const {
if (Dst.getID() == AMDGPU::SGPRRegBankID &&
- Src.getID() == AMDGPU::VGPRRegBankID)
+ Src.getID() == AMDGPU::VGPRRegBankID) {
+ // For boolean values, we can do a v_cmp to "copy" a VGPR to VCC.
+ if (Size == 1)
+ return 1;
+
return std::numeric_limits<unsigned>::max();
+ }
// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
// the valu.
if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
- Src.getID() == AMDGPU::SGPRRegBankID)
+ (Src.getID() == AMDGPU::SGPRRegBankID ||
+ Src.getID() == AMDGPU::VGPRRegBankID))
return std::numeric_limits<unsigned>::max();
return RegisterBankInfo::copyCost(Dst, Src, Size);
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir?rev=350593&r1=350592&r2=350593&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir Mon Jan 7 17:13:20 2019
@@ -84,8 +84,10 @@ body: |
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
- ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
- ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir?rev=350593&r1=350592&r2=350593&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir Mon Jan 7 17:13:20 2019
@@ -84,8 +84,10 @@ body: |
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
- ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
- ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir?rev=350593&r1=350592&r2=350593&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir Mon Jan 7 17:13:20 2019
@@ -83,8 +83,10 @@ body: |
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
- ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
- ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir?rev=350593&r1=350592&r2=350593&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir Mon Jan 7 17:13:20 2019
@@ -84,8 +84,10 @@ body: |
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
- ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
- ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
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