[llvm] r350592 - AMDGPU/GlobalISel: RegBankSelect for carry-in
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 7 17:09:09 PST 2019
Author: arsenm
Date: Mon Jan 7 17:09:09 2019
New Revision: 350592
URL: http://llvm.org/viewvc/llvm-project?rev=350592&view=rev
Log:
AMDGPU/GlobalISel: RegBankSelect for carry-in
I'm not sure we should be allowing the truncate
to s1 for the inputs. It may be necessary to
create a new VCC reg bank.
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=350592&r1=350591&r2=350592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Mon Jan 7 17:09:09 2019
@@ -94,7 +94,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({S32, S1, S64, V2S32});
- getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO})
+ getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
+ G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
.legalFor({{S32, S1}});
setAction({G_BITCAST, V2S16}, Legal);
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=350592&r1=350591&r2=350592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Jan 7 17:09:09 2019
@@ -190,6 +190,31 @@ AMDGPURegisterBankInfo::getInstrAlternat
return AltMappings;
}
+ case TargetOpcode::G_UADDE:
+ case TargetOpcode::G_USUBE:
+ case TargetOpcode::G_SADDE:
+ case TargetOpcode::G_SSUBE: {
+ unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
+ const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
+ getOperandsMapping(
+ {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
+ AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
+ AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
+ AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
+ AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}),
+ 5); // Num Operands
+ AltMappings.push_back(&SSMapping);
+
+ const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
+ getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
+ AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
+ AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
+ AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
+ AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1)}),
+ 5); // Num Operands
+ AltMappings.push_back(&VVMapping);
+ return AltMappings;
+ }
default:
break;
}
@@ -266,7 +291,8 @@ AMDGPURegisterBankInfo::getDefaultMappin
for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
- OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
+ unsigned BankID = Size == 1 ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
+ OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(BankID, Size);
}
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
@@ -372,6 +398,10 @@ AMDGPURegisterBankInfo::getInstrMapping(
case AMDGPU::G_SADDO:
case AMDGPU::G_USUBO:
case AMDGPU::G_SSUBO:
+ case AMDGPU::G_UADDE:
+ case AMDGPU::G_SADDE:
+ case AMDGPU::G_USUBE:
+ case AMDGPU::G_SSUBE:
if (isSALUMapping(MI))
return getDefaultMappingSOP(MI);
LLVM_FALLTHROUGH;
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir?rev=350592&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir Mon Jan 7 17:09:09 2019
@@ -0,0 +1,149 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
+
+---
+name: sadde_s32_sss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: sadde_s32_sss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
+ ; GREEDY-LABEL: name: sadde_s32_sss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
+...
+
+---
+name: sadde_s32_vss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0, $sgpr1
+ ; FAST-LABEL: name: sadde_s32_vss
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
+ ; GREEDY-LABEL: name: sadde_s32_vss
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(s32) = COPY $sgpr1
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
+...
+---
+name: sadde_s32_ssv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $vgpr0
+ ; FAST-LABEL: name: sadde_s32_ssv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
+ ; GREEDY-LABEL: name: sadde_s32_ssv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $vgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
+...
+
+---
+name: sadde_s32_vvs
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0
+ ; FAST-LABEL: name: sadde_s32_vvs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY1]], [[TRUNC]]
+ ; GREEDY-LABEL: name: sadde_s32_vvs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY1]], [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = COPY $sgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
+...
+
+---
+name: sadde_s32_sss_noscc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: sadde_s32_sss_noscc
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY-LABEL: name: sadde_s32_sss_noscc
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir?rev=350592&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir Mon Jan 7 17:09:09 2019
@@ -0,0 +1,149 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
+
+---
+name: ssube_s32_sss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: ssube_s32_sss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
+ ; GREEDY-LABEL: name: ssube_s32_sss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
+...
+
+---
+name: ssube_s32_vss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0, $sgpr1
+ ; FAST-LABEL: name: ssube_s32_vss
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
+ ; GREEDY-LABEL: name: ssube_s32_vss
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(s32) = COPY $sgpr1
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
+...
+---
+name: ssube_s32_ssv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $vgpr0
+ ; FAST-LABEL: name: ssube_s32_ssv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
+ ; GREEDY-LABEL: name: ssube_s32_ssv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $vgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
+...
+
+---
+name: ssube_s32_vvs
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0
+ ; FAST-LABEL: name: ssube_s32_vvs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY1]], [[TRUNC]]
+ ; GREEDY-LABEL: name: ssube_s32_vvs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY1]], [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = COPY $sgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
+...
+
+---
+name: ssubee_s32_sss_noscc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: ssubee_s32_sss_noscc
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY-LABEL: name: ssubee_s32_sss_noscc
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir?rev=350592&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir Mon Jan 7 17:09:09 2019
@@ -0,0 +1,148 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
+---
+name: uadde_s32_sss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: uadde_s32_sss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
+ ; GREEDY-LABEL: name: uadde_s32_sss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
+...
+
+---
+name: uadde_s32_vss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0, $sgpr1
+ ; FAST-LABEL: name: uadde_s32_vss
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
+ ; GREEDY-LABEL: name: uadde_s32_vss
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(s32) = COPY $sgpr1
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
+...
+---
+name: uadde_s32_ssv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $vgpr0
+ ; FAST-LABEL: name: uadde_s32_ssv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
+ ; GREEDY-LABEL: name: uadde_s32_ssv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $vgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
+...
+
+---
+name: uadde_s32_vvs
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0
+ ; FAST-LABEL: name: uadde_s32_vvs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]
+ ; GREEDY-LABEL: name: uadde_s32_vvs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = COPY $sgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
+...
+
+---
+name: uadde_s32_sss_noscc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: uadde_s32_sss_noscc
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY-LABEL: name: uadde_s32_sss_noscc
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir?rev=350592&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir Mon Jan 7 17:09:09 2019
@@ -0,0 +1,149 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
+
+---
+name: usube_s32_sss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: usube_s32_sss
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
+ ; GREEDY-LABEL: name: usube_s32_sss
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
+...
+
+---
+name: usube_s32_vss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0, $sgpr1
+ ; FAST-LABEL: name: usube_s32_vss
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
+ ; GREEDY-LABEL: name: usube_s32_vss
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(s32) = COPY $sgpr1
+ %3:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ %5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
+...
+---
+name: usube_s32_ssv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $vgpr0
+ ; FAST-LABEL: name: usube_s32_ssv
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
+ ; GREEDY-LABEL: name: usube_s32_ssv
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $vgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
+...
+
+---
+name: usube_s32_vvs
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0
+ ; FAST-LABEL: name: usube_s32_vvs
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY1]], [[TRUNC]]
+ ; GREEDY-LABEL: name: usube_s32_vvs
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY1]], [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = COPY $sgpr0
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
+...
+
+---
+name: usube_s32_sss_noscc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST-LABEL: name: usube_s32_sss_noscc
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
+ ; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
+ ; GREEDY-LABEL: name: usube_s32_sss_noscc
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s1) = G_TRUNC %2
+ %4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
+...
More information about the llvm-commits
mailing list