[PATCH] D56305: [AArch64] Support reserving arbitrary general purpose registers

[Tri Vo via Phabricator via llvm-commits]

trong added inline comments.


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Comment at: clang/include/clang/Driver/Options.td:2121
   HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
-foreach i = {1-7,18,20} in
+foreach i = {0-7,9-15,18,20-28} in
   def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group<m_aarch64_Features_Group>,
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With this patch x9-15 can be specified as both reserved and callee-saved. Could you extend test/CodeGen/AArch64/arm64-reserve-call-saved-reg.ll as well? 


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Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:318
 
+  if (Args.hasArg(options::OPT_ffixed_x0))
+    Features.push_back("+reserve-x0");
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What happens (should happen) if we reserve x0 and compile a function with a return value?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56305/new/

https://reviews.llvm.org/D56305