[PATCH] D56306: [X86] Create PMULDQ/PMULUDQ even when the type is illegal. Teach type legalization to split it.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.

Perform the 256-bit AVX1 splitting as part of a post legalize op DAG combine.

This seems to give better opportunities for replacing sign_extend/zero_extend with any_extend when it preceeds a pmuldq/pmuludq.

There are a few slight instruction count regressions where some loads were previously being split and folded directly into pmovzx instructions. Now we are doing one load and then shuffling. This seems to be because generic DAG combine can create a concat of zextload/sextloads when it sees an illegal zero/sign extended load. But this doens't extend to any extend. It's unclear which code is actually better.


Repository:
  rL LLVM

https://reviews.llvm.org/D56306

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-pmuldq.ll
  test/CodeGen/X86/mulvi32.ll
  test/CodeGen/X86/pmul.ll
  test/CodeGen/X86/vector-mul.ll
  test/CodeGen/X86/xop-ifma.ll

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