[PATCH] D56119: [PowerPC] Fix ADDE, SUBE do not know how to promote operator

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: nemanjai, jsji, echristo, steven.zhang, hfinkel, HLJ2009.

This patch is created to fix the Bugzilla bug 39815 <https://bugs.llvm.org/show_bug.cgi?id=39815>.

This patch is to support pormotion integer result for the instruciton `ADDE`, `SUBE`.

Before this fix, for below test case:

  @b = common local_unnamed_addr global i64* null, align 8
  @a = common local_unnamed_addr global i8 0, align 1
  
  define void @testADDEPromoteResult() {
  entry:
    %0 = load i64*, i64** @b, align 8
    %1 = load i64, i64* %0, align 8
    %cmp = icmp ne i64* %0, null
    %conv1 = zext i1 %cmp to i64
    %add = add nsw i64 %1, %conv1
    %2 = trunc i64 %add to i8
    %conv2 = and i8 %2, 5
    store i8 %conv2, i8* @a, align 1
    ret void
  }

We use `llc test.ll` to build the case, then we will get below error:

  PromoteIntegerResult #0: t28: i8,i64 = adde t29, Constant:i8<0>, t24:1
  
  Do not know how to promote this operator!
  UNREACHABLE executed at /home/ken/llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:55!
  Stack dump:
  0.	Program arguments: llc sim.ll
  1.	Running pass 'Function Pass Manager' on module 'sim.ll'.
  2.	Running pass 'PowerPC DAG->DAG Pattern Instruction Selection' on function '@testPromoteOperand'


https://reviews.llvm.org/D56119

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/PowerPC/pr39815.ll


Index: llvm/test/CodeGen/PowerPC/pr39815.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr39815.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+ at b = common dso_local local_unnamed_addr global i64* null, align 8
+ at a = common dso_local local_unnamed_addr global i8 0, align 1
+
+define void @testADDEPromoteResult() {
+entry:
+  %0 = load i64*, i64** @b, align 8
+  %1 = load i64, i64* %0, align 8
+  %cmp = icmp ne i64* %0, null
+  %conv1 = zext i1 %cmp to i64
+  %add = add nsw i64 %1, %conv1
+  %2 = trunc i64 %add to i8
+  %conv2 = and i8 %2, 5
+  store i8 %conv2, i8* @a, align 1
+  ret void
+
+; CHECK-LABEL: @testADDEPromoteResult
+; CHECK:      # %bb.0:
+; CHECK-DAG:   addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc at ha
+; CHECK-DAG:   ld [[REG3:[0-9]+]], [[VAR1]]@toc at l([[REG1]])
+; CHECK-DAG:   lbz [[REG4:[0-9]+]], 0([[REG3]])
+; CHECK-DAG:   addic [[REG5:[0-9]+]], [[REG3]], -1
+; CHECK-DAG:   extsb [[REG6:[0-9]+]], [[REG4]]
+; CHECK-DAG:   addze [[REG7:[0-9]+]], [[REG6]]
+; CHECK-DAG:   addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc at ha
+; CHECK-DAG:   andi. [[REG9:[0-9]+]], [[REG7]], 5
+; CHECK-DAG:   stb [[REG9]], [[VAR2]]@toc at l([[REG8]])
+; CHECK:       blr
+}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -140,6 +140,8 @@
   case ISD::SMULO:
   case ISD::UMULO:       Res = PromoteIntRes_XMULO(N, ResNo); break;
 
+  case ISD::ADDE:
+  case ISD::SUBE:
   case ISD::ADDCARRY:
   case ISD::SUBCARRY:    Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
 


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