[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added a comment.

General question: why 256bit sie of the vector is set is minimal vector register size if the architecture supports 128 bit vectors? TTI should report 128 as the min regsize, not 256. And we don't need all these new options, functions etc.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082