[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)
Anton Afanasyev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 26 04:14:48 PST 2018
anton-afanasyev created this revision.
anton-afanasyev added reviewers: RKSimon, ABataev, dtemirbulatov.
Herald added a subscriber: llvm-commits.
Introduce option -slp-use-semi-reg to SLP vectorizer. This is switched off by
default and is switched on for targets with semi vector register instructions
(like packed horizontal add and sub in SSE). In addition to horizontal instrs
this option triggers optimizations for partial vector operations (for instance,
using low halfs of 128-bit registers xmm0 and xmm1 to multiply <2 x float> by
<2 x float>).
Fixes llvm.org/PR32433
Repository:
rL LLVM
https://reviews.llvm.org/D56082
Files:
include/llvm/Analysis/TargetTransformInfo.h
include/llvm/Analysis/TargetTransformInfoImpl.h
include/llvm/CodeGen/BasicTTIImpl.h
lib/Analysis/TargetTransformInfo.cpp
lib/Target/X86/X86TargetTransformInfo.cpp
lib/Target/X86/X86TargetTransformInfo.h
lib/Transforms/Vectorize/SLPVectorizer.cpp
test/Transforms/SLPVectorizer/X86/addsub.ll
test/Transforms/SLPVectorizer/X86/fptosi.ll
test/Transforms/SLPVectorizer/X86/fptoui.ll
test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
test/Transforms/SLPVectorizer/X86/reorder_phi.ll
test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
test/Transforms/SLPVectorizer/X86/semi-vec-reg-128bit.ll
test/Transforms/SLPVectorizer/X86/shift-lshr.ll
test/Transforms/SLPVectorizer/X86/shift-shl.ll
test/Transforms/SLPVectorizer/X86/sitofp.ll
test/Transforms/SLPVectorizer/X86/tiny-tree.ll
test/Transforms/SLPVectorizer/X86/uitofp.ll
test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
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