[PATCH] D55909: [ExpandISelPseudos] Recompute liveins after introducing a new MBB.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: MatzeB, t.p.northover, sunfish.
Herald added a subscriber: javed.absar.

ExpandISelPSeudos can split existing MBBs, but it does not update the
liveins of the resulting tail block. If physical registers are defined
or live in the original MBB and used in the tail block, we are missing
those in the tail block's liveins.

This patch updates ExpandISelPseudos to add physical registers used and
not defined in the tail block to its liveins.

I am not entirely sure if there are any additional register kinds that
should be ignored here and I am probably missing something else.
I would appreciate any feedback.

The test case is a reduced version of PR35023.


https://reviews.llvm.org/D55909

Files:
  lib/CodeGen/ExpandISelPseudos.cpp
  test/CodeGen/ARM/expand-isel-pseudos-liveins.mir


Index: test/CodeGen/ARM/expand-isel-pseudos-liveins.mir
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/expand-isel-pseudos-liveins.mir
@@ -0,0 +1,38 @@
+# RUN: llc -run-pass=expand-isel-pseudos %s -o - | FileCheck %s
+--- |
+  target triple = "armv6kz"
+
+  define i32 @test1(i32 %x) {
+  entry:
+    unreachable
+  }
+
+...
+---
+name:            test1
+alignment:       2
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+  - { id: 2, class: gpr, preferred-register: '' }
+  - { id: 3, class: gpr, preferred-register: '' }
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $r0, $r1
+    %0:gpr = COPY $r1
+    ADJCALLSTACKDOWN 136, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
+    %1:gpr = COPY $sp
+    %2:gpr = COPY $r0
+    COPY_STRUCT_BYVAL_I32 %2, %0, 72, 8
+    %3:gpr = COPY $r1
+    STRi12 killed %3, %1, 132, 14, $noreg :: (store 4 into stack + 132)
+    ADJCALLSTACKUP 136, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
+    BX_RET 14, $noreg
+...
+# CHECK-LABEL: name: test1
+# CHECK-LABEL: bb.2.entry:
+# CHECK-NEXT: liveins: $r1
Index: lib/CodeGen/ExpandISelPseudos.cpp
===================================================================
--- lib/CodeGen/ExpandISelPseudos.cpp
+++ lib/CodeGen/ExpandISelPseudos.cpp
@@ -14,12 +14,13 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/Support/Debug.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "expand-isel-pseudos"
@@ -65,6 +66,24 @@
           I = NewMBB->getIterator();
           MBBI = NewMBB->begin();
           MBBE = NewMBB->end();
+
+          // Calculate the LiveIns for the new MBB, by adding uses and removing
+          // defs while visiting the instructions in the new MBB in reverse
+          // order.
+          SmallSet<unsigned, 8> LiveIns;
+          for (MachineInstr &MI : reverse(*MBB)) {
+            for (MachineOperand &MOP : reverse(MI.operands())) {
+              if (!MOP.isReg() ||
+                  !TargetRegisterInfo::isPhysicalRegister(MOP.getReg()))
+                continue;
+              if (MOP.isDef())
+                LiveIns.erase(MOP.getReg());
+              else
+                LiveIns.insert(MOP.getReg());
+            }
+          }
+          for (unsigned R : LiveIns)
+            MBB->addLiveIn(R);
         }
       }
     }


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