[llvm] r349716 - AMDGPU: Make i1/i64/v2i32 and/or/xor legal
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 19 17:35:50 PST 2018
Author: arsenm
Date: Wed Dec 19 17:35:49 2018
New Revision: 349716
URL: http://llvm.org/viewvc/llvm-project?rev=349716&view=rev
Log:
AMDGPU: Make i1/i64/v2i32 and/or/xor legal
The 64-bit types do depend on the register bank,
but that's another issue to deal with later.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Wed Dec 19 17:35:49 2018
@@ -34,6 +34,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
const LLT S1 = LLT::scalar(1);
const LLT V2S16 = LLT::vector(2, 16);
+ const LLT V2S32 = LLT::vector(2, 32);
const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64);
@@ -59,9 +60,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
setAction({G_ASHR, S32}, Legal);
setAction({G_SUB, S32}, Legal);
setAction({G_MUL, S32}, Legal);
- setAction({G_AND, S32}, Legal);
- setAction({G_OR, S32}, Legal);
- setAction({G_XOR, S32}, Legal);
+
+ // FIXME: 64-bit ones only legal for scalar
+ getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
+ .legalFor({S32, S1, S64, V2S32});
setAction({G_BITCAST, V2S16}, Legal);
setAction({G_BITCAST, 1, S32}, Legal);
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Wed Dec 19 17:35:49 2018
@@ -357,12 +357,23 @@ AMDGPURegisterBankInfo::getInstrMapping(
switch (MI.getOpcode()) {
default:
return getInvalidInstructionMapping();
+
+ case AMDGPU::G_AND:
+ case AMDGPU::G_OR:
+ case AMDGPU::G_XOR: {
+ unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ if (Size == 1) {
+ OpdsMapping[0] = OpdsMapping[1] =
+ OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
+ break;
+ }
+
+ LLVM_FALLTHROUGH;
+ }
+
case AMDGPU::G_ADD:
case AMDGPU::G_SUB:
case AMDGPU::G_MUL:
- case AMDGPU::G_AND:
- case AMDGPU::G_OR:
- case AMDGPU::G_XOR:
case AMDGPU::G_SHL:
if (isSALUMapping(MI))
return getDefaultMappingSOP(MI);
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir Wed Dec 19 17:35:49 2018
@@ -2,17 +2,72 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_and
+name: test_and_i32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: test_and
+ ; CHECK-LABEL: name: test_and_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_AND %0, %1
$vgpr0 = COPY %2
...
+
+---
+name: test_and_i1
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_and_i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i64 0
+ %3:_(s1) = G_ICMP intpred(ne), %0, %2
+ %4:_(s1) = G_ICMP intpred(ne), %1, %2
+ %5:_(s32) = G_AND %0, %1
+ S_NOP 0, implicit %5
+...
+
+---
+name: test_and_i64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_and_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_AND %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_and_v2i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_and_v2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x s32>) = G_AND %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir Wed Dec 19 17:35:49 2018
@@ -2,17 +2,72 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_or
+name: test_or_i32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: test_or
+ ; CHECK-LABEL: name: test_or_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_OR %0, %1
$vgpr0 = COPY %2
...
+
+---
+name: test_or_i1
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_or_i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: S_NOP 0, implicit [[OR]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i64 0
+ %3:_(s1) = G_ICMP intpred(ne), %0, %2
+ %4:_(s1) = G_ICMP intpred(ne), %1, %2
+ %5:_(s32) = G_OR %0, %1
+ S_NOP 0, implicit %5
+...
+
+---
+name: test_or_i64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_or_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_OR %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_or_v2i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_or_v2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ ; CHECK: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x s32>) = G_OR %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir Wed Dec 19 17:35:49 2018
@@ -2,17 +2,72 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_xor
+name: test_xor_i32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: test_xor
+ ; CHECK-LABEL: name: test_xor_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[XOR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_XOR %0, %1
$vgpr0 = COPY %2
...
+
+---
+name: test_xor_i1
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_xor_i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: S_NOP 0, implicit [[XOR]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i64 0
+ %3:_(s1) = G_ICMP intpred(ne), %0, %2
+ %4:_(s1) = G_ICMP intpred(ne), %1, %2
+ %5:_(s32) = G_XOR %0, %1
+ S_NOP 0, implicit %5
+...
+
+---
+name: test_xor_i64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_xor_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[XOR]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_XOR %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_xor_v2i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_xor_v2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ ; CHECK: [[XOR:%[0-9]+]]:_(<2 x s32>) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[XOR]](<2 x s32>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x s32>) = G_XOR %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir Wed Dec 19 17:35:49 2018
@@ -3,13 +3,13 @@
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
-name: and_ss
+name: and_i32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: and_ss
+ ; CHECK-LABEL: name: and_i32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
@@ -19,13 +19,13 @@ body: |
...
---
-name: and_sv
+name: and_i32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: and_sv
+ ; CHECK-LABEL: name: and_i32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY1]]
@@ -35,13 +35,13 @@ body: |
...
---
-name: and_vs
+name: and_i32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: and_vs
+ ; CHECK-LABEL: name: and_i32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
@@ -52,13 +52,13 @@ body: |
...
---
-name: and_vv
+name: and_i32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: and_vv
+ ; CHECK-LABEL: name: and_i32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY1]]
@@ -66,3 +66,143 @@ body: |
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_AND %0, %1
...
+
+---
+name: and_i1_scc_scc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: and_i1_scc_scc
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
+ ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
+ ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
+ ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s1)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(ne), %0, %2
+ %5:_(s1) = G_ICMP intpred(ne), %1, %2
+ %6:_(s1) = G_AND %4, %5
+ S_NOP 0, implicit %6
+...
+
+---
+name: and_i1_vcc_vcc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: and_i1_vcc_vcc
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
+ ; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s1)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(ne), %0, %2
+ %5:_(s1) = G_ICMP intpred(ne), %1, %2
+ %6:_(s1) = G_AND %4, %5
+ S_NOP 0, implicit %6
+...
+
+---
+name: and_i1_scc_vcc
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; CHECK-LABEL: name: and_i1_scc_vcc
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+ ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
+ ; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
+ ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[ICMP1]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s1)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $vgpr0
+ %2:_(s32) = G_CONSTANT i64 0
+ %4:_(s1) = G_ICMP intpred(ne), %0, %2
+ %5:_(s1) = G_ICMP intpred(ne), %1, %2
+ %6:_(s1) = G_AND %4, %5
+ S_NOP 0, implicit %6
+...
+
+---
+name: and_i1_sgpr_trunc_sgpr_trunc
+legalized: true
+body: |
+ bb.0.entry:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: and_i1_sgpr_trunc_sgpr_trunc
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s1)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s1) = G_TRUNC %0
+ %3:_(s1) = G_TRUNC %1
+ %4:_(s1) = G_AND %2, %3
+ S_NOP 0, implicit %4
+
+...
+
+---
+name: and_i1_trunc_scc
+legalized: true
+body: |
+ bb.0.entry:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: and_i1_trunc_scc
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
+ ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[COPY2]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s1)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s1) = G_TRUNC %0
+ %3:_(s1) = G_ICMP intpred(ne), %0, %1
+ %4:_(s1) = G_AND %2, %3
+ S_NOP 0, implicit %4
+...
+
+---
+name: and_i1_s_trunc_vcc
+legalized: true
+body: |
+ bb.0.entry:
+ liveins: $sgpr0, $vgpr0
+ ; CHECK-LABEL: name: and_i1_s_trunc_vcc
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
+ ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[ICMP]]
+ ; CHECK: S_NOP 0, implicit [[AND]](s1)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $vgpr0
+ %2:_(s1) = G_TRUNC %0
+ %3:_(s1) = G_ICMP intpred(ne), %0, %1
+ %4:_(s1) = G_AND %2, %3
+ S_NOP 0, implicit %4
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir Wed Dec 19 17:35:49 2018
@@ -3,13 +3,13 @@
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
-name: or_ss
+name: or_i32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: or_ss
+ ; CHECK-LABEL: name: or_i32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[COPY]], [[COPY1]]
@@ -19,13 +19,13 @@ body: |
...
---
-name: or_sv
+name: or_i32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: or_sv
+ ; CHECK-LABEL: name: or_i32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY1]]
@@ -35,13 +35,13 @@ body: |
...
---
-name: or_vs
+name: or_i32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: or_vs
+ ; CHECK-LABEL: name: or_i32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
@@ -52,13 +52,13 @@ body: |
...
---
-name: or_vv
+name: or_i32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: or_vv
+ ; CHECK-LABEL: name: or_i32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY1]]
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir?rev=349716&r1=349715&r2=349716&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir Wed Dec 19 17:35:49 2018
@@ -3,13 +3,13 @@
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
-name: xor_ss
+name: xor_i32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: xor_ss
+ ; CHECK-LABEL: name: xor_i32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[COPY]], [[COPY1]]
@@ -19,13 +19,13 @@ body: |
...
---
-name: xor_sv
+name: xor_i32_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: xor_sv
+ ; CHECK-LABEL: name: xor_i32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY1]]
@@ -35,13 +35,13 @@ body: |
...
---
-name: xor_vs
+name: xor_i32_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: xor_vs
+ ; CHECK-LABEL: name: xor_i32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
@@ -52,13 +52,13 @@ body: |
...
---
-name: xor_vv
+name: xor_i32_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: xor_vv
+ ; CHECK-LABEL: name: xor_i32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY1]]
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