[llvm] r349715 - AMDGPU/GlobalISel: Fix ValueMapping tables for i1
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 19 17:33:43 PST 2018
Author: arsenm
Date: Wed Dec 19 17:33:43 2018
New Revision: 349715
URL: http://llvm.org/viewvc/llvm-project?rev=349715&view=rev
Log:
AMDGPU/GlobalISel: Fix ValueMapping tables for i1
This was incorrectly selecting SGPR for any i1 values,
e.g. G_TRUNC to i1 from a VGPR was still an SGPR.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def?rev=349715&r1=349714&r2=349715&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def Wed Dec 19 17:33:43 2018
@@ -16,34 +16,36 @@ namespace AMDGPU {
enum PartialMappingIdx {
None = - 1,
- PM_SGPR1 = 0,
- PM_SGPR16 = 4,
- PM_SGPR32 = 5,
- PM_SGPR64 = 6,
- PM_SGPR128 = 7,
- PM_SGPR256 = 8,
- PM_SGPR512 = 9,
- PM_VGPR1 = 10,
- PM_VGPR16 = 14,
- PM_VGPR32 = 15,
- PM_VGPR64 = 16,
- PM_VGPR128 = 17,
- PM_VGPR256 = 18,
- PM_VGPR512 = 19,
- PM_SGPR96 = 20,
- PM_VGPR96 = 21
+ PM_SGPR1 = 1,
+ PM_SGPR16 = 5,
+ PM_SGPR32 = 6,
+ PM_SGPR64 = 7,
+ PM_SGPR128 = 8,
+ PM_SGPR256 = 9,
+ PM_SGPR512 = 10,
+ PM_VGPR1 = 11,
+ PM_VGPR16 = 15,
+ PM_VGPR32 = 16,
+ PM_VGPR64 = 17,
+ PM_VGPR128 = 18,
+ PM_VGPR256 = 19,
+ PM_VGPR512 = 20,
+ PM_SGPR96 = 21,
+ PM_VGPR96 = 22
};
const RegisterBankInfo::PartialMapping PartMappings[] {
// StartIdx, Length, RegBank
{0, 1, SCCRegBank},
+ {0, 1, SGPRRegBank}, // SGPR begin
{0, 16, SGPRRegBank},
{0, 32, SGPRRegBank},
{0, 64, SGPRRegBank},
{0, 128, SGPRRegBank},
{0, 256, SGPRRegBank},
{0, 512, SGPRRegBank},
- {0, 1, SGPRRegBank},
+
+ {0, 1, VGPRRegBank}, // VGPR begin
{0, 16, VGPRRegBank},
{0, 32, VGPRRegBank},
{0, 64, VGPRRegBank},
@@ -55,33 +57,40 @@ const RegisterBankInfo::PartialMapping P
};
const RegisterBankInfo::ValueMapping ValMappings[] {
+ // SCC
{&PartMappings[0], 1},
+
+ // SGPRs
+ {&PartMappings[1], 1},
+ {nullptr, 0}, // Illegal power of 2 sizes
{nullptr, 0},
{nullptr, 0},
- {nullptr, 0},
- {&PartMappings[1], 1},
{&PartMappings[2], 1},
{&PartMappings[3], 1},
{&PartMappings[4], 1},
{&PartMappings[5], 1},
{&PartMappings[6], 1},
{&PartMappings[7], 1},
+
+ // VGPRs
+ {&PartMappings[8], 1},
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
- {&PartMappings[8], 1},
{&PartMappings[9], 1},
{&PartMappings[10], 1},
{&PartMappings[11], 1},
{&PartMappings[12], 1},
{&PartMappings[13], 1},
{&PartMappings[14], 1},
- {&PartMappings[15], 1}
+ {&PartMappings[15], 1},
+ {&PartMappings[16], 1}
};
enum ValueMappingIdx {
- SGPRStartIdx = 0,
- VGPRStartIdx = 10
+ SCCStartIdx = 0,
+ SGPRStartIdx = 1,
+ VGPRStartIdx = 11
};
const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
@@ -89,7 +98,9 @@ const RegisterBankInfo::ValueMapping *ge
unsigned Idx;
switch (Size) {
case 1:
- Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
+ if (BankID == AMDGPU::SCCRegBankID)
+ return &ValMappings[0];
+ Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
break;
case 96:
Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
@@ -99,6 +110,10 @@ const RegisterBankInfo::ValueMapping *ge
Idx += Log2_32_Ceil(Size);
break;
}
+
+ assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
+ assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
+
return &ValMappings[Idx];
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=349715&r1=349714&r2=349715&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Wed Dec 19 17:33:43 2018
@@ -475,7 +475,7 @@ AMDGPURegisterBankInfo::getInstrMapping(
case AMDGPU::G_FCMP: {
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
- OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 1);
+ OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1);
OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
@@ -515,7 +515,7 @@ AMDGPURegisterBankInfo::getInstrMapping(
unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
Op3Bank == AMDGPU::SGPRRegBankID ?
- AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID;
+ AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir?rev=349715&r1=349714&r2=349715&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir Wed Dec 19 17:33:43 2018
@@ -10,7 +10,7 @@ body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: trunc_i64_to_i32_s
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s32) = G_TRUNC [[COPY]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = G_TRUNC %0
@@ -24,8 +24,63 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: trunc_i64_to_i32_v
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s32) = G_TRUNC [[COPY]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0
...
+---
+name: trunc_i64_to_i1_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: trunc_i64_to_i1_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s1) = G_TRUNC %0
+...
+
+---
+name: trunc_i64_to_i1_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: trunc_i64_to_i1_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s1) = G_TRUNC %0
+...
+
+---
+name: trunc_i32_to_i1_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: trunc_i32_to_i1_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s1) = G_TRUNC %0
+...
+
+---
+name: trunc_i32_to_i1_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: trunc_i32_to_i1_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s1) = G_TRUNC %0
+...
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