[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

[Sanjay Patel via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL349303: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates (authored by spatel, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D55448?vs=178232&id=178393#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55448/new/

https://reviews.llvm.org/D55448

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/ARM/setcc-logic.ll
  llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
  llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
  llvm/trunk/test/CodeGen/X86/avx512-select.ll
  llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-128.ll
  llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll
  llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll
  llvm/trunk/test/CodeGen/X86/psubus.ll
  llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll
  llvm/trunk/test/CodeGen/X86/vector-rotate-256.ll
  llvm/trunk/test/CodeGen/X86/vector-rotate-512.ll

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