[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

The Hexagon tests were meant to check operations on vector predicate registers, so for them to work the inputs need to be vectors of i1 with the lengths that correspond to the lengths of vectors of 8+ bit integers.  The only way to generate such values is do either a compare or a truncate.  Since compare instructions can be fused with logical operations, this leaves truncate as the only option.  With the changes from this patch, truncate is also eliminated, so it appears that these instructions cannot be emitted anymore (from a non-intrinsic code).  With this in mind, I am ok with these changes.


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  https://reviews.llvm.org/D55448/new/

https://reviews.llvm.org/D55448