[PATCH] D55402: [AMDGPU] Simplify negated condition

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 2 inline comments as done.
rampitec added inline comments.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.cpp:1617
+    if (!LIS->hasInterval(Reg))
+      return nullptr;
+    LiveInterval &LI = LIS->getInterval(Reg);
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arsenm wrote:
> Isn’t there a get cached interval or is that only for regunits?
Right, there is getCachedRegUnit(), but not getCachedLiventerval().


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.cpp:1641
+        if (!DefIdx.isValid() ||
+            MDT.dominates(LIS->getInstructionFromIndex(DefIdx),
+                          LIS->getInstructionFromIndex(V->def)))
----------------
arsenm wrote:
> Do you actually need the dominate check? Don’t you implicitly do that when comparing the value numbers?
This is physreg. I need to find a last def. Unfortunately individual reg units get individual LiveRanges, unlike virtual registers. So if I query a def of VCC I am getting two individual VNI for VCC_LO and VCC_HI and need to compare to find a last one. This is checked by negated_cond_vop2_redef_vcc2 test, which miscompiles w/o this check.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55402/new/

https://reviews.llvm.org/D55402