[PATCH] D55516: [GISel]: Add MachineIRBuilder support for passing in Flags while building instructions

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar created this revision.
aditya_nandakumar added reviewers: ab, qcolombet, volkan, bogner, dsanders, aemerson, paquette.

Add the ability to pass in flags to buildInstr calls. Currently no validation is performed but that can be easily performed based on the opcode (if necessary).


Repository:
  rL LLVM

https://reviews.llvm.org/D55516

Files:
  include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  lib/CodeGen/GlobalISel/MachineIRBuilder.cpp


Index: lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
===================================================================
--- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -793,7 +793,8 @@
 
 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
                                                  ArrayRef<DstOp> DstOps,
-                                                 ArrayRef<SrcOp> SrcOps) {
+                                                 ArrayRef<SrcOp> SrcOps,
+                                                 Optional<unsigned> Flags) {
   switch (Opc) {
   default:
     break;
@@ -924,5 +925,7 @@
     Op.addDefToMIB(*getMRI(), MIB);
   for (const SrcOp &Op : SrcOps)
     Op.addSrcToMIB(MIB);
+  if (Flags)
+    MIB->setFlags(*Flags);
   return MIB;
 }
Index: include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -991,8 +991,9 @@
   /// \return a MachineInstrBuilder for the newly created instruction.
 
   MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
-                               const SrcOp &Src1) {
-    return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1});
+                               const SrcOp &Src1,
+                               Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
   }
 
   /// Build and insert \p Res = G_SUB \p Op0, \p Op1
@@ -1007,8 +1008,9 @@
   /// \return a MachineInstrBuilder for the newly created instruction.
 
   MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
-                               const SrcOp &Src1) {
-    return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1});
+                               const SrcOp &Src1,
+                               Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
   }
 
   /// Build and insert \p Res = G_MUL \p Op0, \p Op1
@@ -1022,8 +1024,9 @@
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
-                               const SrcOp &Src1) {
-    return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1});
+                               const SrcOp &Src1,
+                               Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
   }
 
   /// Build and insert \p Res = G_AND \p Op0, \p Op1
@@ -1058,7 +1061,8 @@
   }
 
   virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
-                                         ArrayRef<SrcOp> SrcOps);
+                                         ArrayRef<SrcOp> SrcOps,
+                                         Optional<unsigned> Flags = None);
 };
 
 } // End namespace llvm.


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