[PATCH] D55301: RegAlloc: Allow targets to split register allocation

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D55301#1321550 <https://reviews.llvm.org/D55301#1321550>, @qcolombet wrote:

> Hi Matt,
>
> Have you tried to use combined V+S register classes?
>  By describing such classes, when a S or V register would be split, they would eventually have constraints in that "super" class. Thus, inside of spilling, the splitting mechanism would naturally insert copies of the form `[V|S] = copy V+S` or `V+S = copy [V|S]`, which seem to be what you are trying to achieve. The advantage of such approach is that we would not have to effectively split the allocation.
>
> Cheers,
> -Quentin


I'm not sure I follow this. These aren't spilled with ordinary copies. This uses cross lane instructions to read/write SGPRs into the various lane VGPRs (i.e 64 SGPRs can be spilled to each lane in the wave's VGPR). We also can't legally copy from V to S. Having virtual registers with the combined class doesn't really conceptually make sense for us either (and would probably break every single place that we need to consider these)

This also wouldn't allow us to change the set of reserved registers in the middle of allocation, which is part of the problem.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55301/new/

https://reviews.llvm.org/D55301