[PATCH] D55241: AMDGPU: Should always start from the first register in VGPR indexing.

Changpeng Fang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 5 10:28:44 PST 2018


cfang marked an inline comment as done.
cfang added inline comments.


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:3013
 
-  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
-
-  unsigned SubReg;
-  std::tie(SubReg, Offset)
-    = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
-
+  // SunReg should always be AMDGPU::sub0. The 8-bit m0 field for the index
+  // is unsigned. We can guarantee the index non-negative (if the program
----------------
msearles wrote:
> Typo: SunReg (should be SubReg). Typo is repeated in the second comment block as well.
Thanks. Will correct the typo (if we keep the code this way ).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55241/new/

https://reviews.llvm.org/D55241





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