[PATCH] D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter
Shiva Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 3 23:30:37 PST 2018
shiva0217 created this revision.
shiva0217 added a reviewer: asb.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
As Roger pointed out in https://reviews.llvm.org/rL339654, MCInst return by MCInstBuilder has lifetime limitation.
Repository:
rL LLVM
https://reviews.llvm.org/D55253
Files:
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Index: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -95,7 +95,6 @@
void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- MCInst TmpInst;
MCOperand Func = MI.getOperand(0);
unsigned Ra = (MI.getOpcode() == RISCV::PseudoTAIL) ? RISCV::X6 : RISCV::X1;
uint32_t Binary;
@@ -109,19 +108,23 @@
RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_CALL, Ctx);
// Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
- TmpInst = MCInstBuilder(RISCV::AUIPC)
- .addReg(Ra)
- .addOperand(MCOperand::createExpr(CallExpr));
- Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+ Binary =
+ getBinaryCodeForInstr(MCInstBuilder(RISCV::AUIPC)
+ .addReg(Ra)
+ .addOperand(MCOperand::createExpr(CallExpr)),
+ Fixups, STI);
support::endian::write(OS, Binary, support::little);
if (MI.getOpcode() == RISCV::PseudoTAIL)
// Emit JALR X0, X6, 0
- TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
+ Binary = getBinaryCodeForInstr(
+ MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0),
+ Fixups, STI);
else
// Emit JALR X1, X1, 0
- TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
- Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+ Binary = getBinaryCodeForInstr(
+ MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0), Fixups,
+ STI);
support::endian::write(OS, Binary, support::little);
}
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