[PATCH] D55241: AMDGPU: Should always start from the first register in VGPR indexing.

[Mark Searles via Phabricator via llvm-commits]

msearles added inline comments.


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:3013
 
-  const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
-
-  unsigned SubReg;
-  std::tie(SubReg, Offset)
-    = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
-
+  // SunReg should always be AMDGPU::sub0. The 8-bit m0 field for the index
+  // is unsigned. We can guarantee the index non-negative (if the program
----------------
Typo: SunReg (should be SubReg). Typo is repeated in the second comment block as well.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55241/new/

https://reviews.llvm.org/D55241