[PATCH] D55058: AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts

[Rhys Perry via Phabricator via llvm-commits]

pendingchaos updated this revision to Diff 176282.
pendingchaos added a comment.

Adds a test for the bug.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55058/new/

https://reviews.llvm.org/D55058

Files:
  lib/Target/AMDGPU/SIInstructions.td
  test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll


Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -852,6 +852,8 @@
 def : BitConvert <v2f32, f64, VReg_64>;
 def : BitConvert <f64, v2i32, VReg_64>;
 def : BitConvert <v2i32, f64, VReg_64>;
+def : BitConvert <v4i16, v4f16, VReg_64>;
+def : BitConvert <v4f16, v4i16, VReg_64>;
 
 // FIXME: Make SGPR
 def : BitConvert <v2i32, v4f16, VReg_64>;
Index: test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
===================================================================
--- test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
+++ test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
@@ -0,0 +1,10 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
+
+; CHECK: s_waitcnt
+define <4 x i16> @test(<4 x i32> inreg) #0 {
+  %a = call <4 x half> @llvm.amdgcn.buffer.load.v4f16(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
+  %a_i16 = bitcast <4 x half> %a to <4 x i16>
+  ret <4 x i16> %a_i16
+}
+
+declare <4 x half> @llvm.amdgcn.buffer.load.v4f16(<4 x i32>, i32, i32, i1, i1) #0


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