[PATCH] D54983: Do not insert prefetches with unsupported memory operands.

[Mircea Trofin via Phabricator via llvm-commits]

mtrofin created this revision.
mtrofin added a reviewer: davidxl.
Herald added a subscriber: llvm-commits.

Ignore advices where the memory operand of the 'anchor' instruction
uses unsupported register types.


Repository:
  rL LLVM

https://reviews.llvm.org/D54983

Files:
  lib/Target/X86/X86InsertPrefetch.cpp
  test/CodeGen/X86/insert-prefetch-invalid-instr.afdo
  test/CodeGen/X86/insert-prefetch-invalid-instr.ll
  test/CodeGen/X86/insert-prefetch-no-MachineMemOperand.ll
  test/CodeGen/X86/insert-prefetch-nomemop.afdo


Index: test/CodeGen/X86/insert-prefetch-invalid-instr.ll
===================================================================
--- test/CodeGen/X86/insert-prefetch-invalid-instr.ll
+++ test/CodeGen/X86/insert-prefetch-invalid-instr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-nomemop.afdo | FileCheck %s
+; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-invalid-instr.afdo | FileCheck %s
 ; ModuleID = 'prefetch.cc'
 source_filename = "prefetch.cc"
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -42,5 +42,5 @@
 ;CHECK-LABEL: main:
 ;CHECK:       # %bb.0:
 ;CHECK:       prefetchnta 291
-;CHECK:       prefetchnta 42(%rax,%ymm0)
+;CHECK:       .loc    1 14 3
 ;CHECK-NEXT:  vgatherpf1dpd (%rax,%ymm0) {%k1}
Index: test/CodeGen/X86/insert-prefetch-nomemop.afdo
===================================================================
--- /dev/null
+++ test/CodeGen/X86/insert-prefetch-nomemop.afdo
@@ -1,2 +0,0 @@
-main:0:0
- 6: 0 __prefetch_nta_0:42
\ No newline at end of file
Index: lib/Target/X86/X86InsertPrefetch.cpp
===================================================================
--- lib/Target/X86/X86InsertPrefetch.cpp
+++ lib/Target/X86/X86InsertPrefetch.cpp
@@ -76,6 +76,19 @@
   return std::error_code();
 }
 
+// The prefetch instruction can't take memory operands involving vector
+// registers.
+bool IsMemOpCompatibleWithPrefetch(const MachineInstr &MI, int Op) {
+  unsigned BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
+  unsigned IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
+  return (BaseReg == 0 ||
+          X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) ||
+          X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) &&
+         (IndexReg == 0 ||
+          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
+          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg));
+}
+
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
@@ -182,6 +195,11 @@
       int Offset = X86II::getMemoryOperandNo(Current->getDesc().TSFlags);
       if (Offset < 0)
         continue;
+      unsigned Bias = X86II::getOperandBias(Current->getDesc());
+      int MemOpOffset = Offset + Bias;
+      // FIXME(mtrofin): ORE message when the recommendation cannot be taken.
+      if (!IsMemOpCompatibleWithPrefetch(*Current, MemOpOffset))
+        continue;
       Prefetches.clear();
       if (!findPrefetchInfo(Samples, *Current, Prefetches))
         continue;
@@ -195,8 +213,6 @@
         MachineInstr *PFetch =
             MF.CreateMachineInstr(Desc, Current->getDebugLoc(), true);
         MachineInstrBuilder MIB(MF, PFetch);
-        unsigned Bias = X86II::getOperandBias(Current->getDesc());
-        int MemOpOffset = Offset + Bias;
 
         assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
                X86::AddrIndexReg == 2 && X86::AddrDisp == 3 &&


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