[PATCH] D54957: [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).

[Matt Davis via Phabricator via llvm-commits]

mattd added inline comments.


================
Comment at: tools/llvm-mca/Views/SchedulerStatistics.cpp:87
+  for (const unsigned Buffer : Buffers) {
+    if (Buffer == LQResourceID || Buffer == SQResourceID)
+      continue;
----------------
andreadb wrote:
> mattd wrote:
> > If a target does not define a LQ/SQ resource ID, then SchedulerStats defaults to an ID of '0'.  Is it possible for there to be a valid buffer with a BufferID of 0, or is that some special case?  Our resource Buffer IDs come from an index defined in the processor model: 
> >   `/// An index to the MCProcResourceDesc entry in the processor model.`
> > 
> > 
> ID zero is for the invalid resource. So, it cannot be a buffered resource.
Ok, that's good to know.  Thanks for the clarification.


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  https://reviews.llvm.org/D54957/new/

https://reviews.llvm.org/D54957