[PATCH] D54714: [AMDGPU] Add and update scalar instructions
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 26 08:47:18 PST 2018
arsenm added inline comments.
================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:4538-4539
+ MachineInstr *Xor = nullptr;
+ unsigned Temp = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+ unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+
----------------
grahamsellers wrote:
> arsenm wrote:
> > Should probably use SReg_32_XEXEC
> I couldn't find a SReg_32_XEXEC class, only SReg_32_XEXEC_HI, which seems to only exclude EXEC_LO, or SReg_64_XEXEC, which is 64-bit. Is there any particular reason to avoid EXEC? I can't get the compiler to hit that anyway.
I meant SReg_32_XM0 so vcc_lo/vcc_hi will be allowed, but not m0. Exec doesn't matter much. We reserve exec, so it can never be allocated.
================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:4614-4615
+
+ unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+ unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+
----------------
SReg_32_XM0
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D54714/new/
https://reviews.llvm.org/D54714
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