[PATCH] D52846: [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIFixupVectorISel.cpp:126
+      if (IdxRC != &AMDGPU::VReg_64RegClass &&
+          IdxRC != &AMDGPU::SReg_64RegClass)
+        continue;
----------------
All of these places listing SReg_64* should probably just avoid it since we have so many variants. Something like 
AMDGPU::getRegBitWidth() == 64 && TRI->isSGPRClass(), although maybe we should have an isSGPR64 or something


https://reviews.llvm.org/D52846