[PATCH] D54218: [MachineScheduler] Bias physical register immediate assignments

[Nirav Dave via Phabricator via llvm-commits]

niravd marked 4 inline comments as done.
niravd added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll:20
 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
-; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000
-; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]]
 ; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]:
 define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
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qcolombet wrote:
> Given those are check-DAG, why do we have to update them?
It's from a limitation of FileCheck. As I understand it, FileCheck will greedily match the first of a DAG line if more than one DAG pattern will match. Putting the specialized makes sure we always associate the LOW_REG assignment with it's corresponding pattern.


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Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll:15
+; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
+; SI: buffer_store_dword [[RESULT]]
 ; SI: s_endpgm
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qcolombet wrote:
> Why do we need to weaken those checks?
We don't for this one; I've reverted any file that no longer needs changes. 


Repository:
  rL LLVM

https://reviews.llvm.org/D54218