[PATCH] D54218: [MachineScheduler] Bias physical register immediate assignments

[Nirav Dave via Phabricator via llvm-commits]

niravd updated this revision to Diff 174037.
niravd marked an inline comment as done.
niravd added a comment.

Resolve Quentin's comments. Revert some tests which don't need changes after previous bugfix.


Repository:
  rL LLVM

https://reviews.llvm.org/D54218

Files:
  llvm/include/llvm/CodeGen/MachineScheduler.h
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
  llvm/test/CodeGen/AMDGPU/local-atomics64.ll
  llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
  llvm/test/CodeGen/AMDGPU/ret.ll
  llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
  llvm/test/CodeGen/X86/anyext.ll
  llvm/test/CodeGen/X86/atomic_mi.ll
  llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
  llvm/test/CodeGen/X86/bss_pagealigned.ll
  llvm/test/CodeGen/X86/bypass-slow-division-32.ll
  llvm/test/CodeGen/X86/bypass-slow-division-64.ll
  llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
  llvm/test/CodeGen/X86/cmpxchg16b.ll
  llvm/test/CodeGen/X86/code-model-elf-memset.ll
  llvm/test/CodeGen/X86/combine-srem.ll
  llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
  llvm/test/CodeGen/X86/divrem.ll
  llvm/test/CodeGen/X86/known-bits.ll
  llvm/test/CodeGen/X86/machine-cse.ll
  llvm/test/CodeGen/X86/memset-nonzero.ll
  llvm/test/CodeGen/X86/misched-code-difference-with-debug.ll
  llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
  llvm/test/CodeGen/X86/patchpoint.ll
  llvm/test/CodeGen/X86/pr32282.ll
  llvm/test/CodeGen/X86/pr36865.ll
  llvm/test/CodeGen/X86/pr38865.ll
  llvm/test/CodeGen/X86/scalar_widen_div.ll
  llvm/test/CodeGen/X86/shrink_vmul.ll
  llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
  llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
  llvm/test/CodeGen/X86/speculative-load-hardening.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
  llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
  llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
  llvm/test/DebugInfo/X86/live-debug-values.ll

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