[PATCH] D54419: Preserve MachinePointerInfo offset for unknown base values

[Nikita Popov via Phabricator via llvm-commits]

nikic created this revision.
Herald added subscribers: llvm-commits, javed.absar.

MachineMemOperands store a MachinePointerInfo (with base value and offset) and a base alignment, where the alignment of the actual memory access is computed from the base alignment and the offset. As such, to correctly determine the alignment of a particular load/store it is important to know both the base alignment and the offset.

However, if the base value is not known, then currently `withOffset` calls are simple no-ops, so that effectively the alignment ends up being equal to the base alignment. Fortunately this doesn't happen often due to a combination of a) unspecified bases being uncommon and b) a lot of code contains unnecessary redundant MinAlign calls which end up masking the issue. The attached X86 test case is one instance there this did not occur. Previously the store to `15(%rsp)` was generating a `movaps`.

This patch fixes the issue by preserving the offset even if there is no base value.

I'm not sure if this is the right fix -- I was generally left rather confused trying to understand how alignments are treated in codegen. I got the impression that there is a lot of code that's computing alignments and passing them where really a base alignment is expected.


Repository:
  rL LLVM

https://reviews.llvm.org/D54419

Files:
  include/llvm/CodeGen/MachineMemOperand.h
  test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
  test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir
  test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
  test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
  test/CodeGen/X86/GlobalISel/legalize-undef.mir
  test/CodeGen/X86/byval-odd-size.ll

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