[PATCH] D54073: [x86] allow vector load narrowing with multi-use values

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 173204.
spatel added a comment.

Patch updated:
No code changes; rebased test diffs after https://reviews.llvm.org/rL346433 (improve buildvector lowering) and https://reviews.llvm.org/rL346298 (cosmetic diffs in CHECK lines).
I think the only remaining open question is for pr34653.ll, so I'll take a look at that. IR shows a <38 x double> vector type on an AVX512f target...


https://reviews.llvm.org/D54073

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/Hexagon/HexagonISelLowering.cpp
  test/CodeGen/X86/2012-01-12-extract-sv.ll
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/avx-load-store.ll
  test/CodeGen/X86/avx-vzeroupper.ll
  test/CodeGen/X86/avx512-cvt.ll
  test/CodeGen/X86/avx512-extract-subvector-load-store.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/avx512-shuffles/partial_permute.ll
  test/CodeGen/X86/fma.ll
  test/CodeGen/X86/insert-into-constant-vector.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/nontemporal-loads.ll
  test/CodeGen/X86/oddshuffles.ll
  test/CodeGen/X86/pmaddubsw.ll
  test/CodeGen/X86/pr22774.ll
  test/CodeGen/X86/pr34653.ll
  test/CodeGen/X86/sad.ll
  test/CodeGen/X86/sandybridge-loads.ll
  test/CodeGen/X86/shrink_vmul.ll
  test/CodeGen/X86/shuffle-strided-with-offset-256.ll
  test/CodeGen/X86/shuffle-strided-with-offset-512.ll
  test/CodeGen/X86/shuffle-vs-trunc-256.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/sse2.ll
  test/CodeGen/X86/var-permute-256.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-compare-results.ll
  test/CodeGen/X86/vector-shuffle-combining-avx.ll
  test/CodeGen/X86/vector-trunc.ll
  test/CodeGen/X86/viabs.ll
  test/CodeGen/X86/widen_load-3.ll
  test/CodeGen/X86/x86-interleaved-access.ll