[PATCH] D52010: RegAllocFast: Rewrite and improve

[Matthias Braun via Phabricator via llvm-commits]

MatzeB updated this revision to Diff 172860.
MatzeB added a comment.
Herald added subscribers: jsji, jfb, arphaman, atanasyan, mgrang, jrtc27, nhaehnle, jvesely, nemanjai, sdardis.

- Adapted all the unit tests
- Slight tuning of register hinting code
- Improved allocation heuristic for livethrough and earlyclobber registers, allowing us to allocate more inline assembly constructs consistently (rather than the previous allocator doing it by luck).

This passes `ninja check-llvm` for the first time.

Next steps:

- Code cleanup
- Splitting into multiple commits
- Re-run test-suite benchmarks to gather correctness, compiletime, code size, and execution-speed metrics


Repository:
  rL LLVM

https://reviews.llvm.org/D52010

Files:
  lib/CodeGen/RegAllocFast.cpp
  test/CodeGen/AArch64/arm64-fast-isel-br.ll
  test/CodeGen/AArch64/arm64-fast-isel-call.ll
  test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
  test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
  test/CodeGen/AArch64/br-cond-not-merge.ll
  test/CodeGen/AArch64/cmpxchg-O0.ll
  test/CodeGen/AArch64/fast-isel-cmpxchg.ll
  test/CodeGen/AArch64/fast-isel-sp-adjust.ll
  test/CodeGen/AArch64/regallocfast.mir
  test/CodeGen/AArch64/swift-return.ll
  test/CodeGen/AArch64/swifterror.ll
  test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
  test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  test/CodeGen/AMDGPU/spill-m0.ll
  test/CodeGen/ARM/Windows/alloca.ll
  test/CodeGen/ARM/cmpxchg-O0-be.ll
  test/CodeGen/ARM/cmpxchg-O0.ll
  test/CodeGen/ARM/crash-greedy-v6.ll
  test/CodeGen/ARM/debug-info-blocks.ll
  test/CodeGen/ARM/fast-isel-call.ll
  test/CodeGen/ARM/fast-isel-intrinsic.ll
  test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
  test/CodeGen/ARM/fast-isel-select.ll
  test/CodeGen/ARM/fast-isel-vararg.ll
  test/CodeGen/ARM/ldrd.ll
  test/CodeGen/ARM/swifterror.ll
  test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
  test/CodeGen/Mips/Fast-ISel/memtest1.ll
  test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
  test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
  test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
  test/CodeGen/Mips/atomic.ll
  test/CodeGen/Mips/atomic64.ll
  test/CodeGen/Mips/atomicCmpSwapPW.ll
  test/CodeGen/Mips/branch-relaxation-with-hazard.ll
  test/CodeGen/Mips/dsp-spill-reload.ll
  test/CodeGen/Mips/micromips-eva.mir
  test/CodeGen/PowerPC/addegluecrash.ll
  test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
  test/CodeGen/PowerPC/anon_aggr.ll
  test/CodeGen/PowerPC/fp64-to-int16.ll
  test/CodeGen/PowerPC/spill-nor0.ll
  test/CodeGen/PowerPC/spill-nor0.mir
  test/CodeGen/PowerPC/vsx-args.ll
  test/CodeGen/PowerPC/vsx.ll
  test/CodeGen/SystemZ/swift-return.ll
  test/CodeGen/SystemZ/swifterror.ll
  test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
  test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
  test/CodeGen/X86/atomic32.ll
  test/CodeGen/X86/avx-load-store.ll
  test/CodeGen/X86/avx512-mask-zext-bugfix.ll
  test/CodeGen/X86/crash-O0.ll
  test/CodeGen/X86/extend-set-cc-uses-dbg.ll
  test/CodeGen/X86/fast-isel-nontemporal.ll
  test/CodeGen/X86/fast-isel-select.ll
  test/CodeGen/X86/phys-reg-local-regalloc.ll
  test/CodeGen/X86/pr11415.ll
  test/CodeGen/X86/pr30430.ll
  test/CodeGen/X86/pr32241.ll
  test/CodeGen/X86/pr32256.ll
  test/CodeGen/X86/pr32284.ll
  test/CodeGen/X86/pr32340.ll
  test/CodeGen/X86/pr32345.ll
  test/CodeGen/X86/pr32451.ll
  test/CodeGen/X86/pr32484.ll
  test/CodeGen/X86/pr34592.ll
  test/CodeGen/X86/pr34653.ll
  test/CodeGen/X86/pr38865-2.ll
  test/CodeGen/X86/stack-protector-msvc.ll
  test/CodeGen/X86/swift-return.ll
  test/CodeGen/X86/swifterror.ll
  test/CodeGen/X86/win64_eh.ll
  test/CodeGen/X86/x86-32-intrcc.ll
  test/CodeGen/X86/x86-64-intrcc.ll
  test/DebugInfo/AArch64/frameindices.ll
  test/DebugInfo/AArch64/prologue_end.ll
  test/DebugInfo/ARM/prologue_end.ll
  test/DebugInfo/Mips/delay-slot.ll
  test/DebugInfo/Mips/prologue_end.ll
  test/DebugInfo/X86/dbg-declare-arg.ll
  test/DebugInfo/X86/fission-ranges.ll
  test/DebugInfo/X86/op_deref.ll
  test/DebugInfo/X86/parameters.ll
  test/DebugInfo/X86/pieces-1.ll
  test/DebugInfo/X86/prologue-stack.ll
  test/DebugInfo/X86/spill-indirect-nrvo.ll
  test/DebugInfo/X86/sret.ll

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