[PATCH] D54142: [ARM] Cortex-M4 schedule

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/Target/ARM/ARM.td:980
 
-def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
+def : ProcessorModel<"cortex-m3",   CortexM4Model,      [ARMv7m,
                                                          ProcM3,
----------------
Would it be better to rename CortexM4Model as something more generic e.g. CortexMEfficientModel if it really benefits more than just M4.


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Comment at: lib/Target/ARM/ARMScheduleM4.td:24
+
+let SchedModel = CortexM4Model in {
+
----------------
wrong indentation for let


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Comment at: lib/Target/ARM/ARMScheduleM4.td:26
+
+def M4Unit   : ProcResource<1> { let BufferSize = 0; }
+
----------------
Is this (BufferSize = 0) necessary here for in-order (given, MicroOpBufferSize = 0)?


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Comment at: lib/Target/ARM/ARMScheduleM4.td:46
+
+// Everything else has a Latency of 1
+def : WriteRes<WriteALU, [M4Unit]>;
----------------
You might be able to simplify the code below by creating a new local class as:
class Lat1Type<SchedWrite write> : WriteRes<write, [M4Unit]>;
def : Lat1Type<WriteALU>;
def : Lat1Type<WriteALUsi>;
..
OR
foreach write = [WriteALU, Write ....] in
   def : Lay1Type<write>;


https://reviews.llvm.org/D54142