[PATCH] D54142: [ARM] Cortex-M4 schedule

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Unfortunately, this also increased codesize a little at -Oz, which I will have to look into.



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Comment at: test/CodeGen/Thumb2/ifcvt-no-branch-predictor.ll:122
   store i32 %n, i32* %q, align 4
-  %0 = load i32, i32* %p, align 4
   br label %if.end
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This test in the past, seemed to not take into account that the loads would take two cycles. (Or alternatively, the cycle count for this isn't taking into account that the load will be pipelined, only taking a single cycle). I've changed things to an add to hopefully keep the intent of the test.


https://reviews.llvm.org/D54142