[PATCH] D50633: [AMDGPU] Add new Mode Register pass

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec requested changes to this revision.
rampitec added a comment.
This revision now requires changes to proceed.

You need to model HWREG and add it as impuse to affected instructions and as imdef/out of a setreg.
That is the only correct way to protect it from rescheduling.

That way you will be able to emit setregs early and let some optimizations happen, including those to minimize setreg calls (since setreg is a big performance hit).

Moreover, you may need to split hwreg into several "registers" to track dependencies on individual bits.


Repository:
  rL LLVM

https://reviews.llvm.org/D50633