[PATCH] D50633: [AMDGPU] Add new Mode Register pass

[Tim Corringham via Phabricator via llvm-commits]

timcorringham updated this revision to Diff 172010.
timcorringham added a comment.
Herald added a subscriber: jvesely.

Fixes for observed failures:

- Corrected which instructions are marked as using the double

precision floating point rounding mode flags

- Changed the position where the first setreg in a block is

inserted in order to reduce the risk of hitting a hazard that
may exist at entry to the first block of a shader.


Repository:
  rL LLVM

https://reviews.llvm.org/D50633

Files:
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/SIDefines.h
  lib/Target/AMDGPU/SIInstrFormats.td
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIModeRegister.cpp
  lib/Target/AMDGPU/VOP1Instructions.td
  lib/Target/AMDGPU/VOP2Instructions.td
  lib/Target/AMDGPU/VOP3Instructions.td
  lib/Target/AMDGPU/VOP3PInstructions.td
  test/CodeGen/AMDGPU/mode-register.mir

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