[llvm] r345770 - [SelectionDAG] Handle constant range [0, 1) in lowerRangeToAssertZExt

[Scott Linder via llvm-commits]

Author: scott.linder
Date: Wed Oct 31 12:57:36 2018
New Revision: 345770

URL: http://llvm.org/viewvc/llvm-project?rev=345770&view=rev
Log:
[SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt

lowerRangeToAssertZExt currently relies on something like EarlyCSE having
eliminated the constant range [0,1). At -O0 this leads to an assert.

Differential Revision: https://reviews.llvm.org/D53888

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/test/CodeGen/AMDGPU/zext-lid.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=345770&r1=345769&r2=345770&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Oct 31 12:57:36 2018
@@ -7993,7 +7993,8 @@ SDValue SelectionDAGBuilder::lowerRangeT
     return Op;
 
   APInt Hi = CR.getUnsignedMax();
-  unsigned Bits = Hi.getActiveBits();
+  unsigned Bits = std::max(Hi.getActiveBits(),
+                           static_cast<unsigned>(IntegerType::MIN_INT_BITS));
 
   EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
 

Modified: llvm/trunk/test/CodeGen/AMDGPU/zext-lid.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/zext-lid.ll?rev=345770&r1=345769&r2=345770&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/zext-lid.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/zext-lid.ll Wed Oct 31 12:57:36 2018
@@ -1,4 +1,5 @@
 ; RUN: llc -march=amdgcn < %s | FileCheck %s
+; RUN: llc -O0 -march=amdgcn < %s | FileCheck %s
 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s
 
 ; CHECK-NOT: and_b32
@@ -43,10 +44,21 @@ bb:
   ret void
 }
 
+; When EarlyCSE is not run this call produces a range max with 0 active bits,
+; which is a special case as an AssertZext from width 0 is invalid.
+; OPT-LABEL: @zext_grp_size_1x1x1
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !4
+define amdgpu_kernel void @zext_grp_size_1x1x1(i32 addrspace(1)* nocapture %arg) #0 !reqd_work_group_size !1 {
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp1 = and i32 %tmp, 1
+  store i32 %tmp1, i32 addrspace(1)* %arg, align 4
+  ret void
+}
+
 ; OPT-LABEL: @zext_grp_size_512
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !5
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !5
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !5
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !6
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !6
 define amdgpu_kernel void @zext_grp_size_512(i32 addrspace(1)* nocapture %arg) #1 {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
@@ -74,7 +86,7 @@ entry:
 }
 
 ; OPT-LABEL: @func_test_workitem_id_x_default_range(
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !7
 define void @func_test_workitem_id_x_default_range(i32 addrspace(1)* nocapture %out) #4 {
 entry:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
@@ -96,11 +108,13 @@ attributes #3 = { nounwind readnone }
 attributes #4 = { nounwind }
 
 !0 = !{i32 32, i32 4, i32 1}
+!1 = !{i32 1, i32 1, i32 1}
 
 ; OPT: !0 = !{i32 0, i32 128}
 ; OPT: !1 = !{i32 32, i32 4, i32 1}
 ; OPT: !2 = !{i32 0, i32 32}
 ; OPT: !3 = !{i32 0, i32 4}
 ; OPT: !4 = !{i32 0, i32 1}
-; OPT: !5 = !{i32 0, i32 512}
-; OPT: !6 = !{i32 0, i32 1024}
+; OPT: !5 = !{i32 1, i32 1, i32 1}
+; OPT: !6 = !{i32 0, i32 512}
+; OPT: !7 = !{i32 0, i32 1024}