[PATCH] D53496: AMDGPU: Rewrite SILowerI1Copies to always stay on SALU

[Alexander via Phabricator via llvm-commits]

alex-t added inline comments.


================
Comment at: lib/Target/AMDGPU/SILowerI1Copies.cpp:517
+      for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
+        assert(i + 1 < MI.getNumOperands());
+        unsigned IncomingReg = MI.getOperand(i).getReg();
----------------
How do you suppose this assert can be hit? Given well formed PHI node.


================
Comment at: lib/Target/AMDGPU/SILowerI1Copies.cpp:520
+        MachineBasicBlock *IncomingMBB = MI.getOperand(i + 1).getMBB();
+        MachineInstr *IncomingDef = MRI->getUniqueVRegDef(IncomingReg);
+
----------------
Are you sure that IncomingDef will never be null? What if IncomingReg is the subreg?



Repository:
  rL LLVM

https://reviews.llvm.org/D53496