[llvm] r345190 - [llvm-mca] Replace InstRef::isValid with operator bool. NFC.
Matt Davis via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 24 13:27:47 PDT 2018
Author: mattd
Date: Wed Oct 24 13:27:47 2018
New Revision: 345190
URL: http://llvm.org/viewvc/llvm-project?rev=345190&view=rev
Log:
[llvm-mca] Replace InstRef::isValid with operator bool. NFC.
Modified:
llvm/trunk/tools/llvm-mca/include/Instruction.h
llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp
llvm/trunk/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp
llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp
llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp
llvm/trunk/tools/llvm-mca/lib/Stages/FetchStage.cpp
Modified: llvm/trunk/tools/llvm-mca/include/Instruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/include/Instruction.h?rev=345190&r1=345189&r2=345190&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/include/Instruction.h (original)
+++ llvm/trunk/tools/llvm-mca/include/Instruction.h Wed Oct 24 13:27:47 2018
@@ -444,7 +444,7 @@ public:
const Instruction *getInstruction() const { return Data.second; }
/// Returns true if this references a valid instruction.
- bool isValid() const { return Data.second; }
+ operator bool() const { return Data.second != nullptr; }
/// Invalidate this reference.
void invalidate() { Data.second = nullptr; }
Modified: llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp?rev=345190&r1=345189&r2=345190&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp (original)
+++ llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp Wed Oct 24 13:27:47 2018
@@ -63,7 +63,7 @@ const RetireControlUnit::RUToken &Retire
void RetireControlUnit::consumeCurrentToken() {
const RetireControlUnit::RUToken &Current = peekCurrentToken();
assert(Current.NumSlots && "Reserved zero slots?");
- assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue.");
+ assert(Current.IR && "Invalid RUToken in the RCU queue.");
// Update the slot index to be the next item in the circular queue.
CurrentInstructionSlotIdx += Current.NumSlots;
@@ -73,7 +73,7 @@ void RetireControlUnit::consumeCurrentTo
void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
assert(Queue.size() > TokenID);
- assert(Queue[TokenID].Executed == false && Queue[TokenID].IR.isValid());
+ assert(Queue[TokenID].Executed == false && Queue[TokenID].IR);
Queue[TokenID].Executed = true;
}
Modified: llvm/trunk/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp?rev=345190&r1=345189&r2=345190&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp (original)
+++ llvm/trunk/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp Wed Oct 24 13:27:47 2018
@@ -108,7 +108,7 @@ void Scheduler::promoteToReadySet(SmallV
unsigned RemovedElements = 0;
for (auto I = WaitSet.begin(), E = WaitSet.end(); I != E;) {
InstRef &IR = *I;
- if (!IR.isValid())
+ if (!IR)
break;
// Check if this instruction is now ready. In case, force
@@ -160,7 +160,7 @@ void Scheduler::updateIssuedSet(SmallVec
unsigned RemovedElements = 0;
for (auto I = IssuedSet.begin(), E = IssuedSet.end(); I != E;) {
InstRef &IR = *I;
- if (!IR.isValid())
+ if (!IR)
break;
Instruction &IS = *IR.getInstruction();
if (!IS.isExecuted()) {
Modified: llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp?rev=345190&r1=345189&r2=345190&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp (original)
+++ llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp Wed Oct 24 13:27:47 2018
@@ -154,7 +154,7 @@ Error DispatchStage::cycleStart() {
AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries;
CarryOver -= DispatchedOpcodes;
- assert(CarriedOver.isValid() && "Invalid dispatched instruction");
+ assert(CarriedOver && "Invalid dispatched instruction");
SmallVector<unsigned, 8> RegisterFiles(PRF.getNumRegisterFiles(), 0U);
notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
Modified: llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp?rev=345190&r1=345189&r2=345190&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp (original)
+++ llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp Wed Oct 24 13:27:47 2018
@@ -73,7 +73,7 @@ Error ExecuteStage::issueInstruction(Ins
Error ExecuteStage::issueReadyInstructions() {
InstRef IR = HWS.select();
- while (IR.isValid()) {
+ while (IR) {
if (Error Err = issueInstruction(IR))
return Err;
@@ -107,7 +107,6 @@ Error ExecuteStage::cycleStart() {
return issueReadyInstructions();
}
-
#ifndef NDEBUG
static void verifyInstructionEliminated(const InstRef &IR) {
const Instruction &Inst = *IR.getInstruction();
@@ -121,7 +120,6 @@ static void verifyInstructionEliminated(
}
#endif
-
Error ExecuteStage::handleInstructionEliminated(InstRef &IR) {
#ifndef NDEBUG
verifyInstructionEliminated(IR);
Modified: llvm/trunk/tools/llvm-mca/lib/Stages/FetchStage.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/lib/Stages/FetchStage.cpp?rev=345190&r1=345189&r2=345190&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/lib/Stages/FetchStage.cpp (original)
+++ llvm/trunk/tools/llvm-mca/lib/Stages/FetchStage.cpp Wed Oct 24 13:27:47 2018
@@ -17,19 +17,16 @@
namespace mca {
-bool FetchStage::hasWorkToComplete() const {
- return CurrentInstruction.isValid();
-}
+bool FetchStage::hasWorkToComplete() const { return CurrentInstruction; }
bool FetchStage::isAvailable(const InstRef & /* unused */) const {
- if (CurrentInstruction.isValid())
+ if (CurrentInstruction)
return checkNextStage(CurrentInstruction);
return false;
}
llvm::Error FetchStage::getNextInstruction() {
- assert(!CurrentInstruction.isValid() &&
- "There is already an instruction to process!");
+ assert(!CurrentInstruction && "There is already an instruction to process!");
if (!SM.hasNext())
return llvm::ErrorSuccess();
const SourceRef SR = SM.peekNext();
@@ -45,7 +42,7 @@ llvm::Error FetchStage::getNextInstructi
}
llvm::Error FetchStage::execute(InstRef & /*unused */) {
- assert(CurrentInstruction.isValid() && "There is no instruction to process!");
+ assert(CurrentInstruction && "There is no instruction to process!");
if (llvm::Error Val = moveToTheNextStage(CurrentInstruction))
return Val;
@@ -55,7 +52,7 @@ llvm::Error FetchStage::execute(InstRef
}
llvm::Error FetchStage::cycleStart() {
- if (!CurrentInstruction.isValid())
+ if (!CurrentInstruction)
return getNextInstruction();
return llvm::ErrorSuccess();
}
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