[PATCH] D53562: [ARM] Use the Cortex-A57 sched model for Cortex-A72
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 24 00:43:20 PDT 2018
samparker updated this revision to Diff 170821.
samparker added a comment.
Herald added a subscriber: zzheng.
Added the a72 to a couple of scheduling tests, as well as the basic unroll one.
https://reviews.llvm.org/D53562
Files:
lib/Target/ARM/ARM.td
test/CodeGen/ARM/cortex-a57-misched-alu.ll
test/CodeGen/ARM/cortex-a57-misched-basic.ll
test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
Index: test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
===================================================================
--- test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
+++ test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
@@ -1,5 +1,6 @@
; RUN: opt -mtriple=armv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
+; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a72 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
; RUN: opt -mtriple=thumbv8m -mcpu=cortex-m23 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T1
; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T2
; RUN: opt -mtriple=thumbv7em -mcpu=cortex-m7 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T2
Index: test/CodeGen/ARM/cortex-a57-misched-basic.ll
===================================================================
--- test/CodeGen/ARM/cortex-a57-misched-basic.ll
+++ test/CodeGen/ARM/cortex-a57-misched-basic.ll
@@ -1,5 +1,6 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED
+; RUN: llc < %s -mtriple=armv8-eabi -mcpu=cortex-a72 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; Check the latency for instructions for both generic and cortex-a57.
@@ -35,10 +36,8 @@
; GENERIC: SDIV
; A57_SCHED: SDIV
; A57_SCHED: LDRi12
-; CHECK: ********** INTERVALS **********
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "armv8r-arm-none-eabi"
; Function Attrs: norecurse nounwind readnone
define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr #0 {
Index: test/CodeGen/ARM/cortex-a57-misched-alu.ll
===================================================================
--- test/CodeGen/ARM/cortex-a57-misched-alu.ll
+++ test/CodeGen/ARM/cortex-a57-misched-alu.ll
@@ -1,6 +1,7 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED
+; RUN: llc < %s -mtriple=armv8-eabi -mcpu=cortex-a72 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; Check the latency for ALU shifted operand variants.
;
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -1043,10 +1043,11 @@
FeatureAvoidPartialCPSR,
FeatureCheapPredicableCPSR]>;
-def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
+def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureCrypto,
+ FeatureUseMISched,
FeatureCRC]>;
def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
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