[PATCH] D53562: [ARM] Use the Cortex-A57 sched model for Cortex-A72

[Sam Parker via Phabricator via llvm-commits]

samparker updated this revision to Diff 170820.
samparker added a comment.

Hey Florian,

It was brought to my attention that the scheduler still wasn't enabled because of the missing feature. I've now added this and the geomean improvement is 2.23%. I will shortly add a couple of tests too.


https://reviews.llvm.org/D53562

Files:
  lib/Target/ARM/ARM.td


Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -1043,10 +1043,11 @@
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureCheapPredicableCPSR]>;
 
-def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
+def : ProcessorModel<"cortex-a72", CortexA57Model,      [ARMv8a, ProcA72,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
+                                                         FeatureUseMISched,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,


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