[PATCH] D53160: AMDGPU: Restrict DS load/store vectorizing on SI

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp:296
+
+    KnownBits Bits = computeKnownBits(BasePtr, DL);
+    return Bits.isNonNegative();
----------------
arsenm wrote:
> This seems like an expensive check for this. Is this so important?
I mean I don't understand why this would really matter that much. If we ignore this problem and let it vectorize, the resulting code shouldn't be that different when selection fixes it. The advantage is just making the IR closer to the final hardware instructions, which has minor cost analysis benefits?


Repository:
  rL LLVM

https://reviews.llvm.org/D53160