[PATCH] D52980: [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 8 14:40:45 PDT 2018
RKSimon updated this revision to Diff 168711.
RKSimon added a comment.
Don't ignore 128->256 SIGN/ZERO_EXTENDS like we do for AVX2 - avoid regressions.
Repository:
rL LLVM
https://reviews.llvm.org/D52980
Files:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avg.ll
test/CodeGen/X86/pmaddubsw.ll
test/CodeGen/X86/psubus.ll
test/CodeGen/X86/vector-sext.ll
test/CodeGen/X86/vector-zext.ll
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