[PATCH] D52970: [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 8 11:20:16 PDT 2018


RKSimon updated this revision to Diff 168688.
RKSimon added a comment.

Tweaked load alignment of test - the additional vpmovzxbq /should/ be removable with a suitable demandedelts+demandedbits combine (probably https://reviews.llvm.org/D52935 in reverse).


Repository:
  rL LLVM

https://reviews.llvm.org/D52970

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/pr35443.ll
  test/CodeGen/X86/vector-zext.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D52970.168688.patch
Type: text/x-patch
Size: 14560 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181008/e1cfdddf/attachment.bin>


More information about the llvm-commits mailing list