[PATCH] D52970: [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 8 11:20:16 PDT 2018
RKSimon updated this revision to Diff 168688.
RKSimon added a comment.
Tweaked load alignment of test - the additional vpmovzxbq /should/ be removable with a suitable demandedelts+demandedbits combine (probably https://reviews.llvm.org/D52935 in reverse).
Repository:
rL LLVM
https://reviews.llvm.org/D52970
Files:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avg.ll
test/CodeGen/X86/pr35443.ll
test/CodeGen/X86/vector-zext.ll
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